參數(shù)資料
型號(hào): FLEX10K
廠商: Altera Corporation
英文描述: Embedded Programmable Logic Family
中文描述: 嵌入式可編程邏輯系列
文件頁(yè)數(shù): 26/114頁(yè)
文件大?。?/td> 1422K
代理商: FLEX10K
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Altera Corporation
FLEX 10K Embedded Programmable Logic Family Data Sheet
For improved routability, the row interconnect is comprised of a
combination of full-length and half-length channels. The full-length
channels connect to all LABs in a row; the half-length channels connect to
the LABs in half of the row. The EAB can be driven by the half-length
channels in the left half of the row and by the full-length channels. The
EAB drives out to the full-length channels. In addition to providing a
predictable, row-wide interconnect, this architecture provides increased
routing resources. Two neighboring LABs can be connected using a half-
row channel, thereby saving the other half of the channel for the other half
of the row.
Table 6 summarizes the FastTrack Interconnect resources available in
each FLEX 10K device.
In addition to general-purpose I/O pins, FLEX 10K devices have six
dedicated input pins that provide low-skew signal distribution across the
device. These six inputs can be used for global clock, clear, preset, and
peripheral output enable and clock enable control signals. These signals
are available as control signals for all LABs and IOEs in the device.
The dedicated inputs can also be used as general-purpose data inputs
because they can feed the local interconnect of each LAB in the device.
However, the use of dedicated inputs as data inputs can introduce
additional delay into the control signal network.
Table 6. FLEX 10K FastTrack Interconnect Resources
Device
Rows
Channels per
Row
Columns
Channels per
Column
EPF10K10
EPF10K10A
EPF10K20
EPF10K30
EPF10K30A
EPF10K30E
EPF10K40
EPF10K50
EPF10K50V
EPF10K70
EPF10K100
EPF10K100A
EPF10K130V
EPF10K250A
3
144
24
24
6
6
144
216
24
36
24
24
8
216
216
36
36
24
24
10
9
312
312
52
52
24
24
12
16
20
312
456
52
76
32
40
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