- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299032 > EPM3256ATI144-6 (ALTERA CORP) EE PLD, 6 ns, PQFP144 PDF資料下載
參數(shù)資料
| 型號： | EPM3256ATI144-6 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | EE PLD, 6 ns, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 8/43頁 |
| 文件大?。?/td> | 716K |
| 代理商： | EPM3256ATI144-6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁
16
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Preliminary Information
Programmable
Speed/Power
Control
MAX 3000A devices offer a power-saving mode that supports low-power
operation across user-defined signal paths or the entire device. This
feature allows total power dissipation to be reduced by 50% or more,
because most logic applications require only a small fraction of all gates to
operate at maximum frequency.
The designer can program each individual macrocell in a MAX 3000A
device for either high-speed or low-power operation. As a result, speed-
critical paths in the design can run at high speed, while the remaining
paths can operate at reduced power. Macrocells that run at low power
incur a nominal timing delay adder (tLPA) for the tLAD, tLAC, tIC, tACL, tEN,
and tSEXP parameters.
Output
Conguration
MAX 3000A device outputs can be programmed to meet a variety of
system-level requirements.
MultiVolt I/O Interface
The MAX 3000A device architecture supports the MultiVolt I/O interface
feature, which allows MAX 3000A devices to connect to systems with
differing supply voltages. MAX 3000A devices in all packages can be set
for 2.5-V, 3.3-V, or 5.0-V I/O pin operation. These devices have one set of
VCC pins for internal operation and input buffers (VCCINT), and another
set for I/O output drivers (VCCIO).
Table 7. JTAG Timing Parameters & Values for MAX 3000A Devices
Symbol
Parameter
Min
Max
Unit
tJCP
TCK
clock period
100
ns
tJCH
TCK
clock high time
50
ns
tJCL
TCK
clock low time
50
ns
tJPSU
JTAG port setup time
20
ns
tJPH
JTAG port hold time
45
ns
tJPCO
JTAG port clock to output
25
ns
tJPZX
JTAG port high impedance to valid output
25
ns
tJPXZ
JTAG port valid output to high impedance
25
ns
tJSSU
Capture register setup time
20
ns
tJSH
Capture register hold time
45
ns
tJSCO
Update register clock to output
25
ns
tJSZX
Update register high impedance to valid output
25
ns
tJSXZ
Update register valid output to high impedance
25
ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| EPM3256AQC208-6 | EE PLD, 6 ns, PQFP208 |
| EPM3256AQI208-6 | EE PLD, 6 ns, PQFP208 |
| EPM7128ABC100-6 | EE PLD, 6 ns, PBGA100 |
| EPM7128ABC100-7 | EE PLD, 7.5 ns, PBGA100 |
| EPM7128ABI100-10 | EE PLD, 10 ns, PBGA100 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EPM32CGR2ACL-3555 | 功能描述:撥動開關(guān) SEALED OI RoHS:否 制造商:C&K Components 觸點(diǎn)形式:DPDT 開關(guān)功能:ON - ON - ON 電流額定值: 電壓額定值 AC:20 V 電壓額定值 DC:20 V 功率額定值:0.4 VA 端接類型:V-Bracket 安裝風(fēng)格: 端子密封:Epoxy 觸點(diǎn)電鍍:Gold 照明:Not Illuminated |
| EPM32CXX6ACK | 功能描述:按鈕開關(guān) SEALED OI RoHS:否 制造商:C&K Components 觸點(diǎn)形式:2 NC - 2 NO 開關(guān)功能:ON ? OFF 電流額定值:4 A 電壓額定值 AC:12 V to 250 V 電壓額定值 DC:12 V to 50 V 功率額定值: 安裝風(fēng)格:Through Hole 照明:Illuminated 照明顏色:None IP 等級:IP 40 端接類型:Solder 觸點(diǎn)電鍍:Silver 執(zhí)行器:Square 蓋顏色: 封裝: 可燃性等級:UL 94 V-0 |
| EPM3512A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family |
| EPM3512AFC25610 | 制造商:Altera Corporation 功能描述: |
| EPM3512AFC256-10 | 功能描述:CPLD - 復(fù)雜可編程邏輯器件 CPLD - MAX 3000A 512 Macro 208 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數(shù)量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數(shù)量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。