參數(shù)資料
型號(hào): EPM3256ATI144-6
廠商: ALTERA CORP
元件分類: PLD
英文描述: EE PLD, 6 ns, PQFP144
封裝: TQFP-144
文件頁(yè)數(shù): 39/43頁(yè)
文件大小: 716K
代理商: EPM3256ATI144-6
Altera Corporation
5
MAX 3000A Programmable Logic Device Family Data Sheet
Preliminary Information
The MAX 3000A architecture includes four dedicated inputs that can be
used as general-purpose inputs or as high-speed, global control signals
(clock, clear, and two output enable signals) for each macrocell and I/O
pin. Figure 1 shows the architecture of MAX 3000A devices.
Figure 1. MAX 3000A Device Block Diagram
Logic Array Blocks
The MAX 3000A device architecture is based on the linking of
high-performance LABs. LABs consist of 16-macrocell arrays, as shown in
Figure 1. Multiple LABs are linked together via the PIA, a global bus that
is fed by all dedicated input pins, I/O pins, and macrocells.
Each LAB is fed by the following signals:
s
36 signals from the PIA that are used for general logic inputs
s
Global controls that are used for secondary register functions
6
INPUT/GCLRn
6 Output Enables
16
36
16
I/O
Control
Block
LAB C
LAB D
I/O
Control
Block
6
16
36
16
I/O
Control
Block
LAB A
Macrocells
1 to 16
LAB B
I/O
Control
Block
6
PIA
INPUT/GCLK1
INPUT/OE2/GCLK2
INPUT/OE1
4 to 16 I/O
4 to 16
Macrocells
17 to 32
Macrocells
33 to 48
Macrocells
49 to 64
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