參數(shù)資料
型號(hào)： EPM3256ATI144-6
廠商： ALTERA CORP
元件分類： PLD
英文描述： EE PLD, 6 ns, PQFP144
封裝： TQFP-144
文件頁(yè)數(shù)： 3/43頁(yè)
文件大?。?/td> 716K
代理商： EPM3256ATI144-6
Altera Corporation
11
MAX 3000A Programmable Logic Device Family Data Sheet
Preliminary Information
Figure 6. I/O Control Block of MAX 3000A Devices
When the tri-state buffer control is connected to ground, the output is
tri-stated (high impedance) and the I/O pin can be used as a dedicated
input. When the tri-state buffer control is connected to VCC, the output is
enabled.
The MAX 3000A architecture provides dual I/O feedback, in which
macrocell and pin feedbacks are independent. When an I/O pin is
configured as an input, the associated macrocell can be used for buried
logic.
In-System
Programma-
bility (ISP)
MAX 3000A devices can be programmed in-system via an industry-
standard 4-pin IEEE Std. 1149.1-1990 (JTAG) interface. ISP offers quick,
efficient iterations during design development and debugging cycles. The
MAX 3000A architecture internally generates the high programming
voltages required to program its EEPROM cells, allowing in-system
programming with only a single 3.3-V power supply. During in-system
programming, the I/O pins are tri-stated and weakly pulled-up to
eliminate board conflicts. The pull-up value is nominally 50 k
.
From
Macrocell
Slew-Rate Control
To PIA
To Other I/O Pins
6 Global
Output Enable Signals
PIA
VCC
Open-Drain Output
OE Select Multiplexer
GND
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