參數(shù)資料
型號(hào): EPM3256ATI144-6
廠商: ALTERA CORP
元件分類: PLD
英文描述: EE PLD, 6 ns, PQFP144
封裝: TQFP-144
文件頁數(shù): 12/43頁
文件大小: 716K
代理商: EPM3256ATI144-6
2
Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Preliminary Information
...and More
Features
s
Programmable macrocell flipflops with individual clear, preset,
clock, and clock enable controls
s
Programmable power-saving mode for a power reduction of over
50% in each macrocell
s
Configurable expander product-term distribution, allowing up to
32 product terms per macrocell
s
Programmable security bit for protection of proprietary designs
s
Enhanced architectural features, including:
6 pin- or logic-driven output enable signals
Two global clock signals with optional inversion
Enhanced interconnect resources for improved routability
Programmable output slew-rate control
s
Software design support and automatic place-and-route provided by
the Altera MAX+PLUS II development system for Windows-based
PCs and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC
System/6000 workstations, and the QuartusTM development system
for Windows-based PCs and Sun SPARCstation and HP 9000
Series 700/800 workstations
s
Additional design entry and simulation support provided by EDIF
2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM),
Verilog HDL, VHDL, and other interfaces to popular EDA tools from
third-party manufacturers such as Cadence, Exemplar Logic, Mentor
Graphics, OrCAD, Synopsys, Synplicity, and VeriBest
s
Programming support with Altera’s Master Programming Unit
(MPU), MasterBlasterTM communications cable, ByteBlasterMVTM
parallel port download cable, BitBlasterTM serial download cable as
well as programming hardware from third-party manufacturers and
any in-circuit tester that supports JamTM Files (.jam), Jam Byte-Code
Files (.jbc), or Serial Vector Format Files (.svf)
General
Description
MAX 3000A devices are low-cost, high-performance devices based on
Altera’s MAX architecture. Fabricated with advanced CMOS technology,
the EEPROM-based MAX 3000A devices operate with a 3.3-V supply
voltage and provide 600 to 5,000 usable gates, ISP, pin-to-pin delays as
fast as 4.5 ns, and counter speeds of up to 192.3 MHz. MAX 3000A devices
in the -4, -5, -6, -7, and -10 speed grades are compatible with the timing
requirements of the PCI Special Interest Group (PCI SIG) PCI Local Bus
Specification, Revision 2.2. See Table 2.
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