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參數資料
| 型號： | EPM3256ATI144-6 |
| 廠商： | ALTERA CORP |
| 元件分類： | PLD |
| 英文描述： | EE PLD, 6 ns, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數： | 34/43頁 |
| 文件大?。?/td> | 716K |
| 代理商： | EPM3256ATI144-6 |
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Altera Corporation
MAX 3000A Programmable Logic Device Family Data Sheet
Preliminary Information
MAX 3000A devices contain 32 to 256 macrocells, combined into groups
of 16 macrocells called logic array blocks (LABs). Each macrocell has a
programmable-AND/fixed-OR array and a configurable register with
independently programmable clock, clock enable, clear, and preset
functions. To build complex logic functions, each macrocell can be
supplemented with shareable expander and high-speed parallel expander
product terms to provide up to 32 product terms per macrocell.
MAX 3000A devices provide programmable speed/power optimization.
Speed-critical portions of a design can run at high speed/full power,
while the remaining portions run at reduced speed/low power. This
speed/power optimization feature enables the designer to configure one
or more macrocells to operate at 50% or lower power while adding only a
nominal timing delay. MAX 3000A devices also provide an option that
reduces the slew rate of the output buffers, minimizing noise transients
when non-speed-critical signals are switching. The output drivers of all
MAX 3000A devices can be set for 2.5 V or 3.3 V, and all input pins are
2.5-V, 3.3-V, and 5.0-V tolerant, allowing MAX 3000A devices to be used
in mixed-voltage systems.
MAX 3000A devices are supported by the Quartus and MAX+PLUS II
development systems, which are integrated packages that offer
schematic, text—including VHDL, Verilog HDL, and the Altera
Hardware Description Language (AHDL)—and waveform design entry,
compilation and logic synthesis, simulation and timing analysis, and
device programming. The Quartus and MAX+PLUS II software provides
EDIF 2 0 0 and 3 0 0, LPM, VHDL, Verilog HDL, and other interfaces for
additional design entry and simulation support from other industry-
standard PC- and UNIX-workstation-based EDA tools. The
MAX+PLUS II software runs on Windows-based PCs, as well as Sun
SPARCstation, HP 9000 Series 700/800, and IBM RISC System/6000
workstations. The Quartus software runs on Windows-based PCs, as well
as Sun SPARCstation and HP 9000 Series 700/800 workstations.
f For more information on development tools, see the MAX+PLUS II
Functional
Description
The MAX 3000A architecture includes the following elements:
s
Logic array blocks (LABs)
s
Macrocells
s
Expander product terms (shareable and parallel)
s
Programmable interconnect array
s
I/O control blocks
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相關代理商/技術參數 |
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| EPM32CGR2ACL-3555 | 功能描述:撥動開關 SEALED OI RoHS:否 制造商:C&K Components 觸點形式:DPDT 開關功能:ON - ON - ON 電流額定值: 電壓額定值 AC:20 V 電壓額定值 DC:20 V 功率額定值:0.4 VA 端接類型:V-Bracket 安裝風格: 端子密封:Epoxy 觸點電鍍:Gold 照明:Not Illuminated |
| EPM32CXX6ACK | 功能描述:按鈕開關 SEALED OI RoHS:否 制造商:C&K Components 觸點形式:2 NC - 2 NO 開關功能:ON ? OFF 電流額定值:4 A 電壓額定值 AC:12 V to 250 V 電壓額定值 DC:12 V to 50 V 功率額定值: 安裝風格:Through Hole 照明:Illuminated 照明顏色:None IP 等級:IP 40 端接類型:Solder 觸點電鍍:Silver 執(zhí)行器:Square 蓋顏色: 封裝: 可燃性等級:UL 94 V-0 |
| EPM3512A | 制造商:ALTERA 制造商全稱:Altera Corporation 功能描述:Programmable Logic Device Family |
| EPM3512AFC25610 | 制造商:Altera Corporation 功能描述: |
| EPM3512AFC256-10 | 功能描述:CPLD - 復雜可編程邏輯器件 CPLD - MAX 3000A 512 Macro 208 IOs RoHS:否 制造商:Lattice 系列: 存儲類型:EEPROM 大電池數量:128 最大工作頻率:333 MHz 延遲時間:2.7 ns 可編程輸入/輸出端數量:64 工作電源電壓:3.3 V 最大工作溫度:+ 90 C 最小工作溫度:0 C 封裝 / 箱體:TQFP-100 |
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