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| 型號： | EP910 |
| 廠商： | Altera Corporation |
| 英文描述： | Classic EPLD Family(典型EPLD系列器件) |
| 中文描述： | 經(jīng)典系列可編程邏輯器件（典型可編程邏輯器件系列器件） |
| 文件頁數(shù)： | 5/15頁 |
| 文件大小： | 227K |
| 代理商： | EP910 |
Altera Corporation
973
AN 78: Understanding MAX 5000 & Classic Timing
Figure 1. Single-LAB MAX 5000 Device Timing Model
Figure 2
shows the timing model for the multi-LAB MAX 5000 devices:
the EPM5064, EPM5128, EPM5130, and EPM5192 devices. In multi-LAB
devices, the PIA routes signals between different LABs. All I/O inputs
enter the logic array through the PIA. Signals routed through the PIA
incur an additional delay.
Figure 2. Multi-LAB MAX 5000 Device Timing Model
I/O
Delay
t
IO
Logic Array
Delay
t
LAD
Input
Delay
t
IN
Logic Array
Control Delay
t
LAC
Feedback
Delay
t
FD
Output
Delay
t
OD
t
XZ
t
ZX
Register
Delay
t
RD
t
COMB
t
LATCH
t
CLR
t
PRE
t
SU
t
H
Shared Expander
Delay
t
SEXP
Array
Clock Delay
t
IC
Global Clock
Delay
t
ICS
PIA
Delay
t
PIA
Logic Array
Delay
t
LAD
Input
Delay
t
IN
Logic Array
Control Delay
t
LAC
Feedback
Delay
t
FD
Output
Delay
t
OD
t
XZ
t
ZX
Register
Delay
t
RD
t
COMB
t
LATCH
t
CLR
t
PRE
t
SU
t
H
Shared Expander
Delay
t
SEXP
Array
Clock Delay
t
IC
Global Clock
Delay
t
ICS
I/O
Delay
t
IO
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