參數(shù)資料
型號(hào)： EP910
廠商： Altera Corporation
英文描述： Classic EPLD Family(典型EPLD系列器件)
中文描述： 經(jīng)典系列可編程邏輯器件（典型可編程邏輯器件系列器件）
文件頁(yè)數(shù)： 3/15頁(yè)
文件大?。?/td> 227K
代理商： EP910
Altera Corporation
971
AN 78: Understanding MAX 5000 & Classic Timing
t
FD
Feedback delay. In single-LAB MAX 5000 devices,
t
FD
is the
delay of a macrocell output fed back into the logic array. In
multi-LAB MAX 5000 devices,
t
FD
is the delay of a macrocell
output fed back into the LAB’s logic array or to a PIA input. In
Classic devices,
t
FD
is the delay of a macrocell output fed back
into the logic array.
t
OD
Output buffer and pad delay.
t
XZ
Output buffer disable delay. The delay required for high
impedance to appear at the output pin after the output buffer’s
enable control is disabled.
t
ZX
Output buffer enable delay. The delay required for the output
signal to appear at the output pin after the tri-state buffer’s
enable control is enabled.
External
Timing
Parameters
External timing parameters represent actual pin-to-pin timing
characteristics. Each external timing parameter consists of a combination
of internal timing parameters. The data sheet for each device gives the
values of the external timing parameters. These external timing
parameters are worst-case values, derived from extensive performance
measurements and ensured by testing. All external timing parameters are
shown in bold type. The following list defines external timing parameters
for MAX 5000 and Classic devices. Classic devices include the EP610,
EP610I, EP910, EP910I , and EP1810 devices only.
t
PD1
Dedicated input pin to non-registered output delay. The time
required for a signal on any dedicated input pin to propagate
through the combinatorial logic in a macrocell and appear at an
external device output pin.
t
PD2
I/O pin input to non-registered output delay. The time required
for a signal on any I/O pin input to propagate through the
combinatorial logic in a macrocell and appear at an external
device output pin.
t
PZX
Tri-state to active output delay. The time required for an input
transition to change an external output from a tri-state (high-
impedance) logic level to a valid high or low logic level.
t
PXZ
Active output to tri-state delay. The time required for an input
transition to change an external output from a valid high or low
logic level to a tri-state (high-impedance) logic level.
t
CLR
Time to clear register delay. The time required for a low signal to
appear at the external output, measured from the input
transition.
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參數(shù)描述
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