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參數(shù)資料
| 型號： | EP910 |
| 廠商： | Altera Corporation |
| 英文描述： | Classic EPLD Family(典型EPLD系列器件) |
| 中文描述： | 經(jīng)典系列可編程邏輯器件（典型可編程邏輯器件系列器件） |
| 文件頁數(shù)： | 12/15頁 |
| 文件大小： | 227K |
| 代理商： | EP910 |
980
Altera Corporation
AN 78: Understanding MAX 5000 & Classic Timing
For MAX 5000 devices, the second bit of the
7483
adder macrofunction,
s2
, requires shared expanders. The equations are as follows:
s2 = _LC019;
_LC019 = LCELL(_EQ023 $ _EQ024);
_EQ023 = _X029 & _X030 & _X031;
_X029 = EXP(!b1 & !a1);
_X030 = EXP(!b1 & !c0);
_X031 = EXP(!a1 & !c0);
_EQ024 = _X032 & _X033;
_X032 = EXP(!b2 & a2);
_X033 = EXP(b2 & a2);
Figure 7
shows how you can map the logic structure onto the MAX 5000
architecture with these equations. The timing delay for
s2
in MAX 5000
devices is shown below:
t
IN
+ t
SEXP
+ t
LAD
+ t
COMB
+ t
OD
Figure 7. Adder Equations Mapped to MAX 5000 Architecture
t
LAD
t
COMB
t
OD
t
IN
_X029
_X030
_X031
_X032
_X033
c0
a1
b1
a2
b2
t
SEXP
s2
EXP
EXP
EXP
EXP
EXP
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