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| 型號： | EP910 |
| 廠商： | Altera Corporation |
| 英文描述： | Classic EPLD Family(典型EPLD系列器件) |
| 中文描述： | 經(jīng)典系列可編程邏輯器件（典型可編程邏輯器件系列器件） |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 227K |
| 代理商： | EP910 |
978
Altera Corporation
AN 78: Understanding MAX 5000 & Classic Timing
Examples
The following examples show how to use internal timing parameters to
calculate the delays for real applications.
Example 1: First Bit of 7483 TTL Macrofunction
You can analyze the timing delays for macrofunctions that have been
subjected to minimization and logic synthesis. A MAX+PLUS II Report
File that includes the optional Equations Section lists the synthesized logic
equations for the project. These equations are structured so you can
quickly determine the logic implementation of any signal.
For MAX 5000 devices,
Figure 5
shows part of a
7483
TTL macrofunction
(a 4-bit full adder). The Report File gives the following equations for
s1
,
the least significant bit of the adder:
s1
_LC021 = LCELL (_EQ026 $ C0);
_EQ026 = b1 & !a1
# !b1 & a1;
= OUTPUT (_LC021 , VCC);
Figure 5. Adder Logic Timing for MAX 5000 Architecture
a1
The
combinatorial logic. The combinatorial logic
represents the
XOR
of the intermediate equation
_EQ026
and the carry-in,
c0
. In turn,
_EQ026
is logically equivalent to the
XOR
of inputs
b1
and
a1
.
Therefore, the timing delay for
s1
in MAX 5000 devices is as follows:
s1
output is the output of macrocell 21 (
_LC021
LCELL(_EQ026
), which contains
$
C0)
t
IN
+ t
LAD
+ t
COMB
+ t
OD
NOT
NOT
b1
c0
s1
tLAD
tCOMB
t
OD
tIN
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