參數(shù)資料
型號： EP3SL340F1760C3N
廠商： Altera
文件頁數(shù)： 9/16頁
文件大?。?/td> 0K
描述： IC STRATIX III L 340K 1760-FBGA
產(chǎn)品培訓(xùn)模塊： Three Reasons to Use FPGA's in Industrial Designs
標(biāo)準(zhǔn)包裝： 3
系列： Stratix® III
LAB/CLB數(shù)： 13500
邏輯元件/單元數(shù)： 337500
RAM 位總計(jì)： 18822144
輸入/輸出數(shù)： 1120
電源電壓： 0.86 V ~ 1.15 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 1760-BBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 1760-FCBGA
1–2
Chapter 1: Stratix III Device Family Overview
Features Summary
■
Selectable Core Voltage, available in low-voltage devices (L ordering code suffix),
enables selection of lowest power or highest performance operation
■
Up to 16 global clocks, 88 regional clocks, and 116 peripheral clocks per device
■
Up to 12 phase-locked loops (PLLs) per device that support PLL reconfiguration,
clock switchover, programmable bandwidth, clock synthesis, and dynamic phase
shifting
■
Memory interface support with dedicated DQS logic on all I/O banks
■
Support for high-speed external memory interfaces including DDR, DDR2,
DDR3 SDRAM, RLDRAM II, QDR II, and QDR II+ SRAM on up to 24 modular
I/O banks
■
Up to 1,104 user I/O pins arranged in 24 modular I/O banks that support a wide
range of industry I/O standards
■
Dynamic On-Chip Termination (OCT) with auto calibration support on all I/O
banks
■
High-speed differential I/O support with serializer/deserializer (SERDES) and
dynamic phase alignment (DPA) circuitry for 1.6 Gbps performance
■
Support for high-speed networking and communications bus standards including
SPI-4.2, SFI-4, SGMII, Utopia IV, 10 Gigabit Ethernet XSBI, Rapid I/O, and NPSI
■
The only high-density, high-performance FPGA with support for 256-bit AES
volatile and non-volatile security key to protect designs
■
Robust on-chip hot socketing and power sequencing support
■
Integrated cyclical redundancy check (CRC) for configuration memory error
detection with critical error determination for high availability systems support
■
Built-in error correction coding (ECC) circuitry to detect and correct data errors in
M144K TriMatrix memory blocks
■
Nios II embedded processor support
■
Support for multiple intellectual property megafunctions from Altera MegaCore
functions and Altera Megafunction Partners Program (AMPPSM)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
EP3SL340F1760C3NES 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA 制造商:Altera Corporation 功能描述:IC STRATIX III L FPGA 1760FBGA
EP3SL340F1760C4 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP3SL340F1760C4L 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP3SL340F1760C4LN 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
EP3SL340F1760C4N 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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