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參數(shù)資料
| 型號： | EP3SL340F1760C3N |
| 廠商： | Altera |
| 文件頁數(shù)： | 15/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC STRATIX III L 340K 1760-FBGA |
| 產(chǎn)品培訓模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標準包裝： | 3 |
| 系列： | Stratix® III |
| LAB/CLB數(shù)： | 13500 |
| 邏輯元件/單元數(shù)： | 337500 |
| RAM 位總計： | 18822144 |
| 輸入/輸出數(shù)： | 1120 |
| 電源電壓： | 0.86 V ~ 1.15 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1760-BBGA，F(xiàn)CBGA |
| 供應商設(shè)備封裝： | 1760-FCBGA |
1–8
Chapter 1: Stratix III Device Family Overview
Architecture Features
Stratix III devices have up to 112 DSP blocks. The architectural highlights of the
Stratix III DSP block are the following:
■
High-performance, power optimized, fully pipelined multiplication operations
■
Native support for 9-bit, 12-bit, 18-bit, and 36-bit word lengths
■
Native support for 18-bit complex multiplications
■
Efficient support for floating point arithmetic formats (24-bit for Single Precision
and 53-bit for Double Precision)
■
Signed and unsigned input support
■
Built-in addition, subtraction, and accumulation units to efficiently combine
multiplication results
■
Cascading 18-bit input bus to form tap-delay lines
■
Cascading 44-bit output bus to propagate output results from one block to the next
block
■
Rich and flexible arithmetic rounding and saturation units
■
Efficient barrel shifter support
■
Loopback capability to support adaptive filtering
DSP block multipliers can optionally feed an adder/subtractor or accumulator in the
block depending on user configuration. This option saves ALM routing resources and
increases performance, because all connections and blocks are inside the DSP block.
Additionally, the DSP Block input registers can efficiently implement shift registers
for FIR filter applications, and the Stratix III DSP blocks support rounding and
saturation. The Quartus II software includes megafunctions that control the mode of
operation of the DSP blocks based on user parameter settings.
f For more information, refer to the DSP Blocks in Stratix III Devices chapter.
Clock Networks and PLLs
Stratix III devices provide dedicated Global Clock Networks (GCLKs), Regional Clock
Networks (RCLKs), and Periphery Clock Networks (PCLKs). These clocks are
organized into a hierarchical clock structure that provides up to 104 unique clock
domains (16 GCLK + 88 RCLK) within the Stratix III device and allows for up to 38 (16
GCLK + 22 RCLK) unique GCLK/RCLK clock sources per device quadrant.
Stratix III devices deliver abundant PLL resources with up to 12 PLLs per device and
up to 10 outputs per PLL. Every output can be independently programmed, creating a
unique, customizable clock frequency. Inherent jitter filtration and fine granularity
control over multiply, divide ratios, and dynamic phase-shift reconfiguration provide
the high-performance precision required in today’s high-speed applications. Stratix III
PLLs are feature rich, supporting advanced capabilities such as clock switchover,
reconfigurable phase shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs
can be used for general-purpose clock management supporting multiplication, phase
shifting, and programmable duty cycle. Stratix III PLLs also support external
feedback mode, spread-spectrum input clock tracking, and post-scale counter
cascading.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP3SL340F1760C3NES | 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA 制造商:Altera Corporation 功能描述:IC STRATIX III L FPGA 1760FBGA |
| EP3SL340F1760C4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP3SL340F1760C4L | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP3SL340F1760C4LN | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP3SL340F1760C4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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