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參數(shù)資料
| 型號： | EP3SL340F1760C3N |
| 廠商： | Altera |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 0K |
| 描述： | IC STRATIX III L 340K 1760-FBGA |
| 產(chǎn)品培訓(xùn)模塊： | Three Reasons to Use FPGA's in Industrial Designs |
| 標(biāo)準(zhǔn)包裝： | 3 |
| 系列： | Stratix® III |
| LAB/CLB數(shù)： | 13500 |
| 邏輯元件/單元數(shù)： | 337500 |
| RAM 位總計： | 18822144 |
| 輸入/輸出數(shù)： | 1120 |
| 電源電壓： | 0.86 V ~ 1.15 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1760-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 1760-FCBGA |
Chapter 1: Stratix III Device Family Overview
1–11
Architecture Features
Stratix III devices support configuration data decompression, which saves
configuration memory space and time. This feature allows you to store compressed
configuration data in configuration devices or other memory and transmit this
compressed bitstream to Stratix III devices. During configuration, the Stratix III
device decompresses the bitstream in real time and programs its SRAM cells.
Stratix III devices support decompression in the FPP when using a MAX II
device/microprocessor plus flash, fast AS, and PS configuration schemes. The
Stratix III decompression feature is not available in the FPP when using the enhanced
configuration device and JTAG configuration schemes.
f For more information, refer to the Configuring Stratix III Devices chapter.
Remote System Upgrades
Stratix III devices feature remote system upgrade capability, allowing error-free
deployment of system upgrades from a remote location securely and reliably. Soft
logic (either the Nios embedded processor or user logic) implemented in a Stratix III
device can download a new configuration image from a remote location, store it in
configuration memory, and direct the dedicated remote system upgrade circuitry to
initiate a reconfiguration cycle. The dedicated circuitry performs error detection
during and after the configuration process, and can recover from an error condition
by reverting back to a safe configuration image, and provides error status
information. This dedicated remote system upgrade circuitry is unique to Stratix
series FPGAs and helps to avoid system downtime.
f For more information, refer to the Remote System Upgrades with Stratix III Devices
chapter.
IEEE 1149.1 (JTAG) Boundary-Scan Testing
Stratix III devices support the JTAG IEEE Std. 1149.1 specification. The Boundary-Scan
Test (BST) architecture offers the capability to test pin connections without using
physical test probes and capture functional data while a device is operating normally.
Boundary-scan cells in the Stratix III device can force signals onto pins or capture data
from pin or logic array signals. Forced test data is serially shifted into the
boundary-scan cells. Captured data is serially shifted out and externally compared to
expected results. In addition to BST, you can use the IEEE Std. 1149.1 controller for
Stratix III device in-circuit reconfiguration (ICR).
f For more information, refer to the IEEE 1149.1 (JTAG) Boundary Scan Testing in
Stratix III Devices chapter.
Design Security
Stratix III devices are high-density, high-performance FPGAs with support for 256-bit
volatile and non-volatile security keys to protect designs against copying, reverse
engineering, and tampering. Stratix III devices have the ability to decrypt a
configuration bitstream using the Advanced Encryption Standard (AES) algorithm,
an industry standard encryption algorithm that is FIPS-197 certified and requires a
256-bit security key.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| EP3SL340F1760C3NES | 制造商:Altera Corporation 功能描述:IC FPGA 1120 I/O 1760FBGA 制造商:Altera Corporation 功能描述:IC STRATIX III L FPGA 1760FBGA |
| EP3SL340F1760C4 | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP3SL340F1760C4L | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP3SL340F1760C4LN | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| EP3SL340F1760C4N | 功能描述:FPGA - 現(xiàn)場可編程門陣列 FPGA - Stratix III 13500 LABs 1120 IOs RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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