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EM78569
8-bit Micro-controller
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* This specification is subject to be changed without notice.
8/31/2004 (V4.0)
IOCB (PORTB I/O control, ADC control)
PAGE0 (PORTB I/O control register)
7
6
IOCB7
IOCB6
IOCB5
R/W-1
R/W-1
R/W-1
Bit 0 ~ Bit 7 (IOCB0 ~ IOCB7) : PORTB(0~7) I/O direction control register
0
put the relative I/O pin as output
1
put the relative I/O pin into high impedance
PAGE1 (ADC control bits)
7
6
5
4
IN2
IN1
IN0
ADCLK1 ADCLK0 ADPWR
R/W-0
R/W-0
R/W-0
R/W-0
Bit 0(ADST) : AD converter start to sample
By setting to “1”, the AD will start to sample data. This bit will be cleared by hardware automatically after a
sampling.
Bit 1 : Undefined. This bit is not allow to use.
Bit 2(ADPWR) : AD converter power control, 1/0
enable/disable
Bit 3 ~ Bit 4 (ADCLK0 ~ ADCLK1) : AD circuit ‘s sampling clock source.
For PLL clock = 895.658kHz ~ 17.9MHz (CLK2~CLK0 = 001 ~ 110)
5
4
3
2
1
0
IOCB4
R/W-1
IOCB3
R/W-1
IOCB2
R/W-1
IOCB1
R/W-1
IOCB0
R/W-1
3
2
1
-
0
ADST
R/W-0
R/W-0
R/W-0
ADCLK1 ADCLK0
Sampling rate
74.6K
37.4K
18.7K
9.3K
Operation voltage
0
0
1
1
0
1
0
1
>=3.5V
>=3.0V
>=2.5V
>=2.5V
For PLL clock = 447.829kHz (CLK2~CLK0 = 000)
ADCLK1 ADCLK0
Sampling rate
37.4K
18.7K
9.3K
4.7K
Operation voltage
0
0
1
1
0
1
0
1
>=3.0V
>=3.0V
>=2.5V
>=2.5V
This is a CMOS multi-channel 10-bit successive approximation A/D converter.
Features
74.6kHz maximum conversion speed at 5V.
Adjusted full scale input
External reference voltage input or internal(VDD) reference voltage
6 analog inputs multiplexed into one A/D converter
Power down mode for power saving
A/D conversion complete interrupt
Interrupt register, A/D control and status register, and A/D data register
Fig.14 ADC voltage control logic
Programmable
divider
1/Mx
Divider
Nx
10-bit
ADC
ADCLK1~ADCLK0
fs
ADC output
PLL
ENPLL
CLK2 ~ CLK0
fpll
fadc