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EM78569
8-bit Micro-controller
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* This specification is subject to be changed without notice.
8/31/2004 (V4.0)
If enable PLL, CPU will operate at normal mode (high frequency). Otherwise, it will run at green mode
(low frequency, 32768 Hz).
447.8293kHz ~17.9132MHz
Sub-clock
32.768kHz
switch
0
1
System clock
PLL circuit
ENPLL
CLK2 ~ CLK0
Fig.7 The relation between 32.768kHz and PLL
Bit 7: Unused register. Always keep this bit to 0 or some un-expect error will happen!
The status after wake-up and the wake-up sources list as the table below.
Wakeup signal
SLEEP mode
RA(7,6)=(0,0)
+ SLEP
TCC time out
IOCF bit0=1
COUNTER1 time out
IOCF bit1=1
COUNTER2 time out
IOCF bit2=2
WDT time out
Reset and jump to
address 0
PORT8(0~3)
RE PAGE0 bit3 or
bit4 or bit5 or bit6 = 1
PORT7(0~3)
IOCF bit3 or bit4 or
bit5 =1
<Note> PORT70 's wakeup function is controlled by IOCF bit 3. It's falling edge or rising edge trigger
(controlled by CONT register bit7).
PORT71 's wakeup function is controlled by IOCF bit 4. It’s falling edge trigger.
PORT72~PORT73 's wakeup function is controlled by IOCF. They are falling edge trigger.
PORT80~PORT83’s wakeup function are controlled by RE PAGE0 bit 0 ~ bit 3. They are falling
edge trigger.
PAGE1 (DAC output data register)
7
6
5
4
3
DA7
DA6
DA5
DA4
DA3
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
Bit 0 ~ Bit 7 (DA0 ~ DA7) :
These 8 bit is full DAC data buffer when 8-bit resolution is selected(R7 page1 bit 7
DAREF = 0), or the least significant 8-bit data when 10 bit resolution(DAREF = 1) selected..
No function
No function
No function
Reset and Jump to
address 0
Reset and Jump to
address 0
2
1
0
DA2
R/W-1
DA1
R/W-1
DA0
R/W-1