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參數(shù)資料
| 型號： | ELANSC300-33VI |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁數(shù)： | 74/139頁 |
| 文件大?。?/td> | 1388K |
| 代理商： | ELANSC300-33VI |
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74
élanSC300 Microcontroller Data Sheet
P R E L I M I N A R Y
System Test and Debug
The élanSC300 microcontroller provides test and
debug features compatible with the standard Test Ac-
cess Port (TAP) and Boundary-Scan Architecture
(JTAG).
The test and debug logic contains the following ele-
ments:
n
Five extra pins—TDI, TMS, TCK, TDO, and TRST
(JTAGEN). JTAGEN is dedicated; the other four are
multiplexed.
n
Test Access Port (TAP) controller, which decodes
the inputs on the Test Mode Select (TMS) line to
control test operations.
n
Instruction Register (IR), which accepts instructions
from the Test Data Input (TDI) pin. The instruction
codes select the specific test or debug operation to
be performed or the test data register to be ac-
cessed.
n
Test Data Registers: Boundary Scan Register
(BSR), Device Identification Register (DID), and By-
pass Register (BPR).
Test Access Port (TAP) Controller
The TAP controller is a synchronous, finite state ma-
chine that controls the sequence of operations of the
test logic. The TAP controller changes state in re-
sponse to the rising edge of TCK and defaults to the
test-logic-reset state at power-up. Reinitialization to the
test-logic-reset state is accomplished by holding the
TMS pin High for five TCK periods.
Instruction Register
The Instruction Register is a 4-bit register that allows
instructions to be serially shifted into the device. The in-
struction determines either the test to execute or the
data register to access, or both. The least significant bit
is nearest the TDO output. When the TAP controller en-
ters the capture-IR state, the instruction register is
loaded with the default instruction IDCODE. This is
done to test for faults in the boundary scan connections
at the board level.
Boundary Scan Register
The Boundary Scan Register is a serial shift register
from TDI to TDO, consisting of all the boundary scan
register bits and control cells in each I/O buffer.
Device Identification Register
The Device Identification Register is a 32-bit register
that contains the AMD ID code for the élanSC300 mi-
crocontroller: 195FA003h.
Bypass Register
The Bypass Register provides a path from TDI to TDO
with one clock cycle latency. It helps to bypass a chip
completely while testing boards containing many chips.
Test Access Port Instruction Set
The following instructions are supported:
n
Sample/Preload. This instruction enables the sam-
pling of the contents of the boundary scan registers
as well as the serial loading of the boundary scan
registers through TDI.
n
Bypass. This instruction connects TDI and TDO
through a 1-bit shift register, the Bypass Register.
n
Extest. This instruction enables the parallel loading
of the boundary scan registers. The device inputs
are captured at the input boundary scan cell and the
device outputs are captured at the output boundary
scan cells.
n
IDCODE. This instruction connects the ID code reg-
ister between TDI and TDO. The ID code register
contains the fixed ID code value for the device.
JTAG Software
The élanSC300 microcontroller uses combined bidi-
rectional cells. The total number of shifts required to
load the élanSC300 Boundary Scan Register is 173.
The following table shows the relative position of all the
élanSC300 JTAG cells. Note that:
n
The chain starts at PMC2 (pin 77) connected to TDI.
n
The chain ends at 8042CS (pin 75) connected to
TDO.
n
The control cells are located within the chain, their
relative position being indicated in the table.
n
The MUXed signals (TCK, TDI, TDO, and TMS) are
not part of the cell chain.
n
Control cells are active Low.
n
Refer to Figure 10–22 of the IEEE 1149 standard.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| ELANSC300WW WAF | 制造商:Advanced Micro Devices 功能描述: |
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