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| 型號(hào)： | ELANSC300-33VI |
| 廠商： | Advanced Micro Devices, Inc. |
| 元件分類(lèi)： | 32位微控制器 |
| 英文描述： | Highly Integrated, Low-Power, 32-Bit Microcontroller |
| 中文描述： | 高度集成，低功耗，32位微控制器 |
| 文件頁(yè)數(shù)： | 73/139頁(yè) |
| 文件大?。?/td> | 1388K |
| 代理商： | ELANSC300-33VI |
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élanSC300 Microcontroller Data Sheet
73
P R E L I M I N A R Y
ISA BUS DESCRIPTIONS
The three bus configuration options (Internal LCD con-
troller, local bus, or maximum ISA bus) each support a
somewhat different subset of the ISA bus standard.
The Internal LCD controller option supports the small-
est ISA subset, defined in Table 37.
Notes:
1. These ISA functions are available in this mode as long as
the internal LCD controller is not configured for a dual-
scan LCD panel in which case these pins would be used
as additional data bits for the LCD panel. In Local Bus
mode and Maximum ISA mode, the ISA function is always
available.
The Local Bus configuration supports a larger ISA sub-
set. The additional pins supported are shown in Table
38. The Maximum ISA Bus configuration adds the pins
found in Table .
Table 37.
Internal LCD Controller Bus Mode ISA
Bus Functionality
Pin Name
SA23–SA0
D15–D0
IOCHRDY
RSTDRV
MEMW
MEMR
IOW
IOR
AEN
TC
SYSCLK
I/O
Function
O
System Address Bus
System Data Bus
I/O Channel Ready
System Reset
Memory Write
Memory Read
I/O Write
I/O Read
DMA Address Enable
Terminal Count
System Clock (ISA bus timing is not
derived from this clock)
Interrupt IRQ1
Programmable IRQx
Programmable IRQx
DMA Channel 2 Acknowledge
DMA Channel 2 Request
B
I
O
O
O
O
O
O
O
O
IRQ1
PIRQ0
PIRQ1
DACK2
DRQ2
IOCS16
I
I
I
O
I
I
I/O Device is 16 bits
1
MCS16
I
Memory Device is 16 bits
1
IRQ14
I
Interrupt Request Input
1
SBHE
O
Byte High Enable
1
Video Oscillator (14.336 MHz)/
Serial Port Output
X1OUT
[BAUDOUT]
O
Table 38.
Local Bus Mode Additional ISA Bus
Functionality
Pin Name
IOCHCHK
DRQ1
DACK1
DRQ5
DACK5
IRQ4
IRQ12
IRQ15
I/O
Function
I
ISA I/O Channel Check
DMA Channel 1 Request
DMA Channel 1 Acknowledge
DMA Channel 5 Request
DMA Channel 5 Acknowledge
Interrupt Request Input
Interrupt Request Input
Interrupt Request Input
I
O
I
O
I
I
I
Table 39.
Maximum ISA Bus Mode Additional ISA
Bus Functionality
Pin Name
BALE
DREQ0
DREQ3
DREQ6
DREQ7
DACK0
DACK3
DACK6
DACK7
IRQ7
IRQ9
IRQ11
0WS
LA23–LA17
LMEG
IRQ5
IRQ10
I/O
Function
O
ISA Bus Address Latch Enable
DMA Channel 0 Request
DMA Channel 3 Request
DMA Channel 6 Request
DMA Channel 7 Request
DMA Channel 0 Acknowledge
DMA Channel 3 Acknowledge
DMA Channel 6 Acknowledge
DMA Channel 7 Acknowledge
Interrupt Request Input
Interrupt Request Input
Interrupt Request Input
Zero Wait State Request
ISA Non-Latched Address
ISA Memory Cycle Below 100000h
Interrupt Request Input
Interrupt Request Input
I
I
I
I
O
O
O
O
I
I
I
I
O
O
I
I
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