![](http://datasheet.mmic.net.cn/160000/DSRT-L030-011_datasheet_8669787/DSRT-L030-011_23.png)
RipTide PCI Audio/Comm Device Family Product Description
1167
ROCKWELL PROPRIETARY INFORMATION
23
4.3.4
AC Electrical Characteristics
4.3.4.1
PCI Interface Signals
The PCI interface timing for PCI interface signals (4.2.1) conforms to the PCI Local Bus Specification, Production Version,
Revision 2.1, June 1, 1995.
4.3.4.2
PnP Serial EEPROM Interface Signals
An external 1K bit (64 x 16) PnP serial EEPROM is required only if the product and manufacturers ID for Plug and Play is to
be modified to other than the Rockwell registered IDs. Otherwise, the internal ROM can be used for PnP support to reduce
manufacturing cost. If the EEPROM is not used, specific discrete components must be depopulated (refer to the RipTide
reference design schematic).
The serial EEPROM interface meets the timing requirements of an Atmel AT93C46, Microchip Technology, Inc. 93LC46B, or
equivalent 1K bit (64 x 16) device. Note: Atmel AT93C46 is used, connect pin 6 of the AT93C46 to VCC to select x16
configuration.
The following summarizes timing information for serial EEPROM interface signals.
Symbol
Parameter
Min
Max
Units
tval
CLK to Signal Valid Delay
400
ns
tsu
Input Set-up Time to CLK
100
ns
th
Input Hold Time from CLK
100
ns
4.3.4.3
Codec AC-link Interface Signals
The AC-link timing is described in Section 5.4.5.
4.3.4.4
JTAG Interface
When enabled, the JTAG interface uses the TCK input as its clock. All pins of the device have JTAG implemented. Please
refer to IEEE Std 1149.1 for timing information.
4.3.4.5
Modem DSP Parallel Host Bus Interface
Parameter
Symbol
Min.
Max.
Units
a. Read
Address Setup
TRS
10
–
ns
Chip Select Setup
TCS
0
–
ns
Control Hold
THC
10
–
ns
Read Data Access
TDA
-
35
ns
Read Data Hold
TDHR
10
–
ns
Read Pulse Width
TRR
45
–
ns
b. Write
Address Setup
TRS
10
–
ns
Chip Select Setup
TCS
0
–
ns
Control Hold
THC
10
–
ns
Write Data Setup
TWDS
10
–
ns
Write Data Hold
TWDH
10
–
ns
Write Pulse Width
TWW
45
–
ns