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參數(shù)資料
| 型號： | DSPE56007FJ50 |
| 英文描述： | DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC |
| 中文描述： | 數(shù)字信號處理器| 24位|的CMOS | QFP封裝| 80腳|塑料 |
| 文件頁數(shù)： | 77/83頁 |
| 文件大?。?/td> | 382K |
| 代理商： | DSPE56007FJ50 |
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Design Considerations
Electrical Design Considerations
MOTOROLA
DSP56007/D
4-3
ELECTRICAL DESIGN CONSIDERATIONS
Use the following list of recommendations to assure correct DSP operation:
Provide a low-impedance path from the board power supply to each V
CC
pin on the DSP, and from the board ground to each GND pin.
Use at least four 0.01–0.1
μ
F bypass capacitors positioned as close as
possible to the four sides of the package to connect the V
CC
power source
to GND.
Ensure that capacitor leads and associated printed circuit traces that
connect to the chip V
CC
and GND pins are less than 0.5 in per capacitor
lead.
Use at least a four-layer Printed Circuit Board (PCB) with two inner layers
for V
CC
and GND.
Because the DSP output signals have fast rise and fall times, PCB trace
lengths should be minimal. This recommendation particularly applies to
the address and data buses as well as the IRQA, IRQB, and NMI pins.
Maximum Printed Circuit Board (PCB) trace lengths on the order of
6 inches are recommended.
Consider all device loads as well as parasitic capacitance due to PCB
traces when calculating capacitance. This is especially critical in systems
with higher capacitive loads that could create higher transient currents in
the V
CC
and GND circuits.
All inputs must be terminated (i.e., not allowed to float) using CMOS
levels, except as noted in
Section 1
.
Take special care to minimize noise levels on the V
CCP
and GND
P
pins.
If multiple DSP56007 devices are on the same board, check for cross-talk
or excessive spikes on the supplies due to synchronous operation of the
devices.
CAUTION
This device contains protective circuitry to guard against
damage due to high static voltage or electrical fields.
However, normal precautions are advised to avoid
application of any voltages higher than maximum rated
voltages to this high-impedance circuit. Reliability of
operation is enhanced if unused inputs are tied to an
appropriate logic voltage level (e.g., either GND or V
CC
).
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