參數(shù)資料
型號(hào)： DSPE56007FJ50
英文描述： DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述： 數(shù)字信號(hào)處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù)： 3/83頁
文件大?。?/td> 382K
代理商： DSPE56007FJ50
DSP56007
Features
MOTOROLA
DSP56007/D
iii
FEATURES
Digital Signal Processing Core
Efficient, object code compatible with the 24-bit DSP56000 core family engine
Up to 44 Million Instructions Per Second (MIPS)—22.7 ns instruction cycle at
88 MHz
Highly parallel instruction set with unique DSP addressing modes
Two 56-bit accumulators including extension byte
Parallel 24
×
24-bit multiply-accumulate in 1 instruction cycle (2 clock cycles)
Double precision 48
×
48-bit multiply with 96-bit result in 6 instruction cycles
56-bit addition/ subtraction in 1 instruction cycle
Fractional and integer arithmetic with support for multiprecision arithmetic
Hardware support for block floating-point Fast Fourier Transforms (FFT)
Hardware nested DO loops
Zero-overhead fast interrupts (2 instruction cycles)
Four 24-bit internal data buses and three 16-bit internal address buses for
simultaneous accesses to one program and two data memories
Fabricated in high-density CMOS
Memory
On-chip modified Harvard architecture, which permits simultaneous accesses
to program and two data memories
Bootstrap loading from Serial Host Interface or External Memory Interface
Table 1
Memory Configuration (Word width is 24 bits)
Mode
Program
X Data
Y Data
Bootstrap
ROM
PE
ROM
RAM
ROM
RAM
ROM
RAM
0
1
6400
5120
None
1024
512
512
1024
1024
512
512
2176
1152
52
52
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