參數(shù)資料
型號(hào)： DSPE56007FJ50
英文描述： DSP|24-BIT|CMOS|QFP|80PIN|PLASTIC
中文描述： 數(shù)字信號(hào)處理器| 24位|的CMOS | QFP封裝| 80腳|塑料
文件頁數(shù)： 40/83頁
文件大?。?/td> 382K
代理商： DSPE56007FJ50
2-16
DSP56007/D
MOTOROLA
Specifications
External Memory Interface (EMI) DRAM Refresh Timing
EXTERNAL MEMORY INTERFACE (EMI) DRAM REFRESH TIMING
(C
L
= 50pF + 2 TTL Loads)
Table 2-9
External Memory Interface (EMI) DRAM Refresh Timing
No.
Characteristics
Sym.
Timing
Mode
Exp.
50 MHz
66 MHz
88 MHz
Unit
Min Max Min Max Min Max
81 RAS Deassertation to
RAS Assertion
82 CAS Deassertation to
CAS Assertion
83 Refresh Cycle Time
t
RP
slow
fast
1
6
×
T
C
– 7
4
×
T
C
– 7
5
×
T
C
– 7
3
×
T
C
– 7
13
×
T
C
9
×
T
C
7
×
T
C
– 9
5
×
T
C
– 9
5
×
T
C
– 5
3
×
T
C
– 5
113
73
—
—
84
—
—
—
61.2
—
—
—
ns
ns
T
CPN
slow
fast
1
slow
fast
1
slow
fast
1
slow
fast
1
93
53
260
180
131
91
95
55
—
—
—
—
—
—
—
—
71
—
197
—
97
—
70
—
—
—
—
—
—
—
—
—
49.8
—
147.7
—
70.5
—
51.8
—
—
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
t
RC
84 RAS Assertion Pulse
Width
85 RAS Deassertation to
RAS Assertion for
Refresh Cycle
2
86 CAS Assertion to RAS
Assertion on Refresh
Cycle
87 RAS Assertion to CAS
Deassertation on
Refresh Cycle
88 RAS Deassertation to
CAS Assertion on a
Refresh Cycle
89 CAS Deassertation to
Data Not Valid
t
RAS
t
RP
T
CSR
T
C
– 7
13
—
8
—
4.4
—
ns
T
CHR
slow
fast
1
7
×
T
C
– 15
5
×
T
C
– 15
125
85
—
—
91
—
—
—
64.5
—
—
—
ns
ns
t
RPC
slow
fast
1
5
×
T
C
– 11
3
×
T
C
– 11
89
49
—
—
65
—
—
—
45.8
—
—
—
ns
ns
t
OFF
0
0
—
0
—
0
—
ns
Note:
1.
2.
Fast mode is not available for operating frequencies above 50 MHz.
This happens when a Refresh Cycle is followed by an Access Cycle.
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