參數(shù)資料
型號(hào)： DSP56F805E
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 13/56頁(yè)
文件大小： 415K
代理商： DSP56F805E
Interrupt and Program Control Signals
56F805 Technical Data, Rev. 15
Freescale Semiconductor
13
2.5 Interrupt and Program Control Signals
Table 2-9 Interrupt and Program Control Signals
No. of
Pins
Signal
Name
Signal
Type
State
During
Reset
Signal Description
1
IRQA
Input
(Schmitt)
Input
External Interrupt Request A
—The IRQA input is a synchronized
external interrupt request indicating an external device is requesting
service. It can be programmed to be level-sensitive or
negative-edge-triggered.
1
IRQB
Input
(Schmitt)
Input
External Interrupt Request B
—The IRQB input is an external
interrupt request indicating an external device is requesting service.
It can be programmed to be level-sensitive or
negative-edge-triggered.
1
RESET
Input
(Schmitt)
Input
Reset
—This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed in
the Reset state. A Schmitt trigger input is used for noise immunity.
When the RESET pin is deasserted, the initial chip operating mode
is latched from the EXTBOOT pin. The internal reset signal will be
deasserted synchronous with the internal clocks, after a fixed
number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and it is
necessary not to reset the OnCE/JTAG module. In this case, assert
RESET, but do not assert TRST.
1
RSTO
Output
Output
Reset Output
—This output reflects the internal reset state of the
chip.
1
EXTBOOT
Input
(Schmitt)
Input
External Boot
—This input is tied to V
DD
to force device to boot
from off-chip memory. Otherwise, it is tied to V
SS
.
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DSP56F805FV80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
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