參數(shù)資料
型號(hào)： DSP56F805E
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 11/56頁(yè)
文件大?。?/td> 415K
代理商： DSP56F805E
Clock and Phase Locked Loop Signals
56F805 Technical Data, Rev. 15
Freescale Semiconductor
11
2.3 Clock and Phase Locked Loop Signals
2.4 Address, Data, and Bus Control Signals
Table 2-5 PLL and Clock
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
1
EXTAL
Input
Input
External Crystal Oscillator Input
—This input should be
connected to an 8MHz external crystal or ceramic resonator. For
more information, please refer to
Section 3.5
.
1
XTAL
Input/O
utput
Chip-driven
Crystal Oscillator Output
—This output should be connected to
an 8MHz external crystal or ceramic resonator. For more
information, please refer to
Section 3.5
.
This pin can also be connected to an external clock source. For
more information, please refer to
Section 3.5.3
.
1
CLKO
Output
Chip-driven
Clock Output
—This pin outputs a buffered clock signal. By
programming the CLKOSEL[4:0] bits in the CLKO Select
Register (CLKOSR), the user can select between outputting a
version of the signal applied to XTAL and a version of the
device’s master clock at the output of the PLL. The clock
frequency on this pin can also be disabled by programming the
CLKOSEL[4:0] bits in CLKOSR.
Table 2-6 Address Bus Signals
No. of
Pins
Signal
Name
Signal
Type
State During
Reset
Signal Description
6
A0–A5
Output
Tri-stated
Address Bus
—A0–A5 specify the address for external
Program or Data memory accesses.
2
A6–A7
GPIOE2
–
GPIOE3
Output
Input/O
utput
Tri-stated
Input
Address Bus
—A6–A7 specify the address for external
Program or Data memory accesses.
Port E GPIO
—These two General Purpose I/O (GPIO) pins
can be individually programmed as input or output pins.
After reset, the default state is Address Bus.
8
A8–A15
GPIOA0
–
GPIOA7
Output
Input/O
utput
Tri-stated
Input
Address Bus
—A8–A15 specify the address for external
Program or Data memory accesses.
Port A GPIO
—These eight General Purpose I/O (GPIO) pins
can be individually be programmed as input or output pins.
After reset, the default state is Address Bus.
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DSP56F805EVMUM 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56F805 Evaluation Module Hardware User＇s Manual
DSP56F805FV80 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 80Mhz/ 40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F805FV80E 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 80Mhz/40MIPS RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT
DSP56F805FV80E 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor IC DSP Type:Cor
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