參數(shù)資料
型號(hào)： DSP56852E
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 4/48頁(yè)
文件大小： 731K
代理商： DSP56852E
56852 Technical Data, Rev. 8
4
Freescale Semiconductor
Part 1 Overview
1.1 56852 Features
1.1.1
Core
Efficient 16-bit engine with dual Harvard architecture
120 Million Instructions Per Second (MIPS) at 120MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four (4) 36-bit accumulators including extension bits
16-bit bidirectional shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three (3) internal address buses and one (1) external address bus
Four (4) internal data buses and one (1) external data bus
Instruction set supports both DSP and controller functions
Four (4) hardware interrupt levels
Five (5) software interrupt levels
Controller-style addressing modes and instructions for compact code
Efficient C Compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/Enhanced OnCE debug programming interface
1.1.2
Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
On-chip memory includes:
— 6K
×
16-bit Program SRAM
— 4K
×
16-bit Data SRAM
— 1K
×
16-bit Boot ROM
21 External Memory Address lines, 16 data lines and four (4) programmable chip select signals
1.1.3
Peripheral Circuits for DSP56852
General Purpose 16-bit Quad Timer with two external pins*
One (1) Serial Communication Interface (SCI)*
One (1) Serial Port Interface (SPI) or one (1) Improved Synchronous Serial Interface (ISSI) module*
Interrupt Controller
Computer Operating Properly (COP)/Watchdog Timer
JTAG/Enhanced On-Chip Emulation (EOnCE) for unobtrusive, real-time debugging
81-pin MAPBGA package
Up to 11 GPIO
* Each peripheral I/O can be used alternately as a General Purpose I/O if not needed
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