參數(shù)資料
型號(hào)： DSP56852E
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 16/48頁(yè)
文件大?。?/td> 731K
代理商： DSP56852E
56852 Technical Data, Rev. 8
16
Freescale Semiconductor
Table 4-1 Absolute Maximum Ratings
Characteristic
Symbol
Min
Max
Unit
Supply voltage, core
V
DD1
1.
V
DD
must not exceed V
DDIO
V
DDIO
and V
DDA
must not differ by more that 0.5V
V
SS
– 0.3
V
SS
+ 2.0
V
Supply voltage, IO
Supply voltage, analog
V
DDIO2
V
DDIO2
2.
V
SSIO
– 0.3
V
SSA
– 0.3
V
SSIO
+ 4.0
V
DDA
+ 4.0
V
Digital input voltages
Analog input voltages (XTAL, EXTAL)
V
IN
V
INA
V
SSIO
– 0.3
V
SSA
– 0.3
V
SSIO
+ 5.5
V
DDA
+ 0.3
V
Current drain per pin excluding V
DD
, V
SS,
V
DDA
,
V
SSA,
V
DDIO
, V
SSIO
I
—
10
mA
Junction temperature
T
J
-40
120
°C
Storage temperature range
T
STG
-55
150
°C
Table 4-2 Recommended Operating Conditions
Characteristic
Symbol
Min
Max
Unit
Supply voltage for Logic Power
V
DD
1.62
1.98
V
Supply voltage for I/O Power
V
DDIO
3.0
3.6
V
Supply voltage for Analog Power
V
DDA
3.0
3.6
V
Ambient operating temperature
T
A
-40
85
°C
PLL clock frequency
1
1.
selected. The actual frequency depends on the source clock frequency and programming of the CGM module.
Assumes clock source is direct clock to EXTAL or crystal oscillator running 2-4MHz PLL must be enabled, locked, and
f
pll
—
240
MHz
Operating Frequency
2
2.
Master clock is derived from one of the following four sources:
f
clk
= f
xtal
when the source clock is the direct clock to EXAL
f
clk
= f
pll
when PLL is selected
f
clk
= f
osc
when the source clock is the crystal oscillator and PLL is not selected
f
clk
= f
extal
when the source clock is the direct clock to EXAL and PLL is not selected
f
op
—
120
MHz
Frequency of peripheral bus
f
ipb
—
60
MHz
Frequency of external clock
f
clk
—
240
MHz
Frequency of oscillator
f
osc
2
4
MHz
Frequency of clock via XTAL
f
xtal
—
240
MHz
Frequency of clock via EXTAL
f
extal
2
4
MHz
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