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參數(shù)資料
| 型號： | DSP56852E |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 16-bit Digital Signal Controllers |
| 中文描述： | 16位數(shù)字信號控制器 |
| 文件頁數(shù)： | 12/48頁 |
| 文件大小： | 731K |
| 代理商： | DSP56852E |
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56852 Technical Data, Rev. 8
12
Freescale Semiconductor
E3
WR
Output
Bus Control–Write Enable (WR)
— is asserted during external
memory write cycles. When WR is asserted low, pins D0–D15 become
outputs and the controller puts data on the bus. When WR is
deasserted high, the external data is latched inside the external device.
When WR is asserted, it qualifies the A0–A15 pins. WR can be
connected directly to the WE pin of a Static RAM.
B4
RXD
GPIOE0
Input
Input/Output
SCI Receive Data (RXD)—
This input receives byte-oriented serial data
and transfers it to the SCI receive shift register.
Port E GPIO (0)
—A general purpose I/O pin.
D4
TXD
GPIOE1
Output(Z)
Input/Output
SCI Transmit Data (TXD)—
This signal transmits data from the SCI
transmit data register.
Port E GPIO (1)
—A general purpose I/O pin.
B2
GPIOC0
STXD
Input
/Output
Output
Port C GPIO (0)
—This pin is a General Purpose I/O (GPIO) pin when
the SSI is not in use.
SSI Transmit Data (STXD)—
This output pin transmits serial data from
the SSI Transmitter Shift Register.
A2
GPIOC1
SRXD
Input
/Output
Input
Port C GPIO (1)
—This pin is a General Purpose I/O (GPIO) pin when
the SSI is not in use.
SSI Receive Data (SRXD)—
This input pin receives serial data and
transfers the data to the SSI Receive Shift Register.
A3
SCLK
GPIOC2
STCK
Input
/Output
Input/Output
Input/Output
SPI Serial Clock (SCLK)
—In Master mode, this pin serves as an
output, clocking slaved listeners. In Slave mode, this pin serves as the
data clock input.
Port C GPIO (2)
—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
SSI Serial Transfer Clock (STCK)—
This bidirectional pin provides the
serial bit rate clock for the transmit section of the SSI. The clock signal
can be continuous or gated.
B3
SS
GPIOC3
STFS
Input
Input/Output
Input/Output
SPI Slave Select (SS)
—In Master mode, this pin is used to arbitrate
multiple masters. In Slave mode, this pin is used to select the slave.
Port C GPIO (3)
—This pin is a General Purpose I/O (GPIO) pin that
can individually be programmed as input or output pin.
SSI Serial Transfer Frame Sync
(STFS)
—
This bidirectional pin is
used to count the number of words in a frame while transmitting. A
programmable frame rate divider and a word length divider are used for
frame rate sync signal generation.
Table 3-1. 56852 Signal and Package Information for the 81-pin MAPBGA (Continued)
Pin No.
Signal Name
Type
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| DSP56852VFE | 16-bit Digital Signal Controllers |
| DSP56853E | 16-bit Digital Signal Controllers |
| DSP56853FG120 | 16-bit Digital Signal Controllers |
| DSP56853FGE | 16-bit Digital Signal Controllers |
| DSP56854FGE | 16-bit Digital Signal Controllers |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56852EVM | 制造商:Freescale Semiconductor 功能描述:IC's |
| DSP56852EVMUM | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56852 Evaluation Module User＇s Manual |
| DSP56852PB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:56852 Digital Signal Processor Product Brief |
| DSP56852UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:16-Bit Digital Signal Processor User＇s Manual |
| DSP56852UMAD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP56852UM Rev 2.0 Addendum |
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