參數(shù)資料
型號(hào)： DSP56852E
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁(yè)數(shù)： 23/48頁(yè)
文件大?。?/td> 731K
代理商： DSP56852E
External Memory Interface Timing
56852 Technical Data, Rev. 8
Freescale Semiconductor
23
Figure 4-9 External Clock Timing
4.6 External Memory Interface Timing
The External Memory Interface is designed to access static memory and peripheral devices.
Figure 4-10
shows sample timing and parameters that are detailed in
Table 4-7
.
The timing of each parameter consists of both a fixed delay portion and a clock related portion; as well as
user controlled wait states. The equation:
t = D + P * (M + W)
should be used to determine the actual time of each parameter. The terms in the above equation are defined as:
t
parameter delay time
D
fixed portion of the delay, due to on-chip path delays.
P
the period of the system clock, which determines the execution rate of the part (i.e. when the device is
operating at 120 MHz, P = 8.33 ns).
M Fixed portion of a clock period inherent in the design. This number is adjusted to account for possible
clock duty cycle derating.
W the sum of the applicable wait state controls. See the “Wait State Controls” column of
Table 4-7
for
the applicable controls for each parameter. See the EMI chapter of the 83x Peripheral Manual for
details of what each wait state field controls.
Table 4-6 PLL Timing
Operating Conditions: V
SS
= V
SSIO
= V
SSA
= 0V, V
DD
= 1.62-1.98V, V
DDIO
= V
DDA
= 3.0–3.6V, T
A
= –40
°
to +120
°
C, C
L
￡ 50pF, f
op
= 120MHz
Characteristic
Symbol
Min
Typ
Max
Unit
External reference crystal frequency for the PLL
1
1.
The PLL is optimized for 4MHz input crystal.
An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly.
f
osc
2
4
4
MHz
PLL output frequency
f
clk
40
—
240
MHz
PLL stabilization time
2
2.
This is the minimum time required after the PLL setup is changed to ensure reliable operation.
t
plls
—
1
10
ms
External
Clock
V
IH
V
IL
Note: The midpoint is V
IL
+ (V
IH
– V
IL
)/2.
90%
50%
10%
90%
50%
10%
t
PW
t
PW
t
fall
t
rise
相關(guān)PDF資料
PDF描述
DSP56852VFE 16-bit Digital Signal Controllers
DSP56853E 16-bit Digital Signal Controllers
DSP56853FG120 16-bit Digital Signal Controllers
DSP56853FGE 16-bit Digital Signal Controllers
DSP56854FGE 16-bit Digital Signal Controllers
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56852EVM 制造商:Freescale Semiconductor 功能描述:IC's
DSP56852EVMUM 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:DSP56852 Evaluation Module User＇s Manual
DSP56852PB 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:56852 Digital Signal Processor Product Brief
DSP56852UM 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:16-Bit Digital Signal Processor User＇s Manual
DSP56852UMAD 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:DSP56852UM Rev 2.0 Addendum
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*