參數(shù)資料
型號(hào)： DSP56800ERM
廠商： 飛思卡爾半導(dǎo)體(中國)有限公司
英文描述： 16-bit Digital Signal Controllers
中文描述： 16位數(shù)字信號(hào)控制器
文件頁數(shù)： 75/124頁
文件大小： 1880K
代理商： DSP56800ERM
Register Descriptions
56F8013 Technical Data, Rev. 2
Freescale Semiconductor
Preliminary
75
6.3.9.11 PWM IPBus Clock Enable (PWM)—Bit 0
Each bit controls clocks to the indicated peripheral.
0 = The clock is not provided to the peripheral (the peripheral is disabled)
1 = Clocks are enabled
6.3.10
I/O Short Address Location Register (SIM_IOSAHI and
SIM_IOSALO)
The I/O Short Address Location registers are used to specify the memory referenced via the I/O short
address mode. The I/O short address mode allows the instruction to specify the lower six bits of address;
the upper address bits are not directly controllable. This register set allows limited control of the full
address, as shown in
Figure 6-12
.
Figure 6-12 I/O Short Address Determination
With this register set, an interrupt driver can set the SIM_IOSALO register pair to point to its peripheral
registers and then use the I/O Short addressing mode to reference them. The ISR should restore this register
to its previous contents prior to returning from interrupt.
Note:
The default value of this register set points to the EOnCE registers.
Note:
The pipeline delay between setting this register set and using short I/O addressing with the new value
is five instruction cycles.
Figure 6-13 I/O Short Address Location High Register (SIM_IOSAHI)
Base + $D
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ISAL[23:22]
Write
RESET
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
Instruction Portion
“
Hard Coded” Address Portion
6 Bits from I/O Short Address Mode Instruction
16 Bits from SIM_IOSALO Register
2 bits from SIM_IOSAHI Register
Full 24-Bit for Short I/O Address
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