參數(shù)資料
型號(hào): DSP56321VL240
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類: 數(shù)字信號(hào)處理
英文描述: 24-Bit Digital Signal Processor
中文描述: 24位數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 8/84頁(yè)
文件大?。?/td> 898K
代理商: DSP56321VL240
DSP56321 Technical Data, Rev. 11
1-2
Freescale Semiconductor
Signals/Connections
Figure 1-1.
Signals Identified by Functional Group
Notes:
1.
The HI08 port supports a non-multiplexed or a multiplexed bus, single or double data strobe (DS), and single or
double host request (HR) configurations. Since each of these modes is configured independently, any combination of
these modes is possible. These HI08 signals can also be configured alternatively as GPIO signals (PB[0–15]).
Signals with dual designations (for example, HAS/HAS) have configurable polarity.
The ESSI0, ESSI1, and SCI signals are multiplexed with the Port C GPIO signals (PC[0–5]), Port D GPIO signals
(PD[0–5]), and Port E GPIO signals (PE[0–2]), respectively.
TIO[0–2] can be configured as GPIO signals.
2.
3.
DSP56321
24
18
External
Address Bus
External
Data Bus
External
Bus
Control
Enhanced
Synchronous Serial
Interface Port 0
(ESSI0)
2
Timers
3
OnCE/
JTAG Port
Power Inputs:
Core Logic
I/O
Address Bus
Data Bus
Bus Control
HI08
ESSI/SCI/Timer
A[0–17]
D[0–23]
AA[0–3]
RD
WR
TA
BR
BG
BB
TCK
TDI
TDO
TMS
TRST
DE
V
CCQL
V
CCQH
V
CCA
V
CCD
V
CCC
V
CCH
V
CCS
5
3
Serial
Communications
Interface (SCI) Port
2
4
2
2
Grounds:
Ground plane
GND
66
Interrupt/
Mode Control
MODA
MODB
MODC
MODD
RESET
PINIT
Host
Interface
(HI08) Port
1
Non-Multiplexed
Bus
H[0–7]
HA0
HA1
HA2
HCS/HCS
Single DS
HRW
HDS/HDS
Single HR
HREQ/HREQ
HACK/HACK
RXD
TXD
SCLK
SC0[0–2]
SCK0
SRD0
STD0
TIO0
TIO1
TIO2
8
3
3
EXTAL
XTAL
Clock
Enhanced
Synchronous Serial
Interface Port 1
(ESSI1)
2
SC1[0–2]
SCK1
SRD1
STD1
3
Multiplexed
Bus
HAD[0–7]
HAS/HAS
HA8
HA9
HA10
Double DS
HRD/HRD
HWR/HWR
Double HR
HTRQ/HTRQ
HRRQ/HRRQ
Port B
GPIO
PB[0–7]
PB8
PB9
PB10
PB13
PB11
PB12
PB14
PB15
Port E GPIO
PE0
PE1
PE2
Port C GPIO
PC[0–2]
PC3
PC4
PC5
Port D GPIO
PD[0–2]
PD3
PD4
PD5
Timer GPIO
TIO0
TIO1
TIO2
Port A
4
IRQA
IRQB
IRQC
IRQD
RESET
NMI
During Reset
After Reset
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