
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
A-7
M_CD EQU $FFF            
M_COD EQU 12              
M_SCP EQU 13              
M_RCM EQU 14              
M_TCM EQU 15              
; Clock Divider Mask (CD0-CD11)
; Clock Out Divider
; Clock Prescaler
; Receive Clock Mode Source Bit
; Transmit Clock Source Bit
;------------------------------------------------------------------------
;
;       EQUATES for Synchronous Serial Interface (SSI)
;
;------------------------------------------------------------------------
;
;       Register Addresses Of SSI0 
M_TX00 EQU $FFFFBC         
M_TX01 EQU $FFFFBB         
M_TX02 EQU $FFFFBA         
M_TSR0 EQU $FFFFB9         
M_RX0 EQU $FFFFB8         
M_SSISR0 EQU $FFFFB7 
M_CRB0 EQU $FFFFB6         
M_CRA0 EQU $FFFFB5         
M_TSMA0 EQU $FFFFB4         
M_TSMB0 EQU $FFFFB3         
M_RSMA0 EQU $FFFFB2         
M_RSMB0 EQU $FFFFB1         
; SSI0 Transmit Data Register 0
; SSIO Transmit Data Register 1
; SSIO Transmit Data Register 2
; SSI0 Time Slot Register
; SSI0 Receive Data Register
; SSI0 Status Register
; SSI0 Control Register B
; SSI0 Control Register A
; SSI0 Transmit Slot Mask Register A
; SSI0 Transmit Slot Mask Register B
; SSI0 Receive Slot Mask Register A
; SSI0 Receive Slot Mask Register B
;       Register Addresses Of SSI1                                        
M_TX10 EQU $FFFFAC         
; SSI1 Transmit Data Register 0
M_TX11 EQU $FFFFAB         
; SSI1 Transmit Data Register 1
M_TX12 EQU $FFFFAA         
; SSI1 Transmit Data Register 2
M_TSR1 EQU $FFFFA9         
; SSI1 Time Slot Register
M_RX1 EQU $FFFFA8         
; SSI1 Receive Data Register
M_SSISR1 EQU $FFFFA7 
; SSI1 Status Register
M_CRB1 EQU $FFFFA6         
; SSI1 Control Register B
M_CRA1 EQU $FFFFA5         
; SSI1 Control Register A
M_TSMA1 EQU $FFFFA4         
; SSI1 Transmit Slot Mask Register A
M_TSMB1 EQU $FFFFA3         
; SSI1 Transmit Slot Mask Register B
M_RSMA1 EQU $FFFFA2         
; SSI1 Receive Slot Mask Register A
M_RSMB1 EQU $FFFFA1         
; SSI1 Receive Slot Mask Register B
;       SSI Control Register A Bit Flags
M_PM EQU $FF            
M_PSR EQU 11              
M_DC EQU $1F000          
M_ALC EQU 18         
M_WL EQU $380000         
M_SSC1 EQU 22         
; Prescale Modulus Select Mask (PM0-PM7)              
; Prescaler Range       
; Frame Rate Divider Control Mask (DC0-DC7)
; Alignment Control (ALC)
; Word Length Control Mask (WL0-WL7)
; Select SC1 as TR #0 drive enable (SSC1)
;       SSI Control Register B Bit Flags                                   
M_OF EQU $3              
M_OF0 EQU 0               
M_OF1 EQU 1               
M_SCD EQU $1C             
M_SCD0 EQU 2 
M_SCD1 EQU 3               
M_SCD2 EQU 4               
M_SCKD EQU 5               
M_SHFD EQU 6               
M_FSL EQU $180            
M_FSL0 EQU 7               
; Serial Output Flag Mask
; Serial Output Flag 0                     
; Serial Output Flag 1                     
; Serial Control Direction Mask            
; Serial Control 0 Direction                
; Serial Control 1 Direction               
; Serial Control 2 Direction               
; Clock Source Direction
; Shift Direction                          
; Frame Sync Length Mask (FSL0-FSL1)
; Frame Sync Length 0