參數(shù)資料
型號： DSP56321VL240
廠商： 飛思卡爾半導體(中國)有限公司
元件分類： 數(shù)字信號處理
英文描述： 24-Bit Digital Signal Processor
中文描述： 24位數(shù)字信號處理器
文件頁數(shù)： 41/84頁
文件大小： 898K
代理商： DSP56321VL240
AC Electrical Characteristics
DSP56321 Technical Data, Rev. 11
Freescale Semiconductor
2-21
2.4.7
SCI Timing
Table 2-11.
SCI Timings
No.
Characteristics
1
Symbol
Expression
200 MHz
220 MHz
240 MHz
275 MHz
Uni
t
Min
Max
Min
Max
Min
Max
Min
Max
400
Synchronous clock cycle
t
SCC2
16
×
T
C
80.0
—
72.8
—
66.7
—
58.0
—
ns
401
Clock low period
t
SCC
/2
10.0
30.0
—
26.4
—
23.4
—
19.0
—
ns
402
Clock high period
t
SCC
/2
10.0
30.0
—
26.4
—
23.4
—
19.0
—
ns
403
Output data setup to
clock falling edge
(internal clock)
t
SCC
/4 + 0.5
×
T
C
17.0
5.5
—
3.5
—
1.76
—
–0.68
—
ns
404
Output data hold after
clock rising edge (internal
clock)
t
SCC
/4
1.5
×
T
C
13
—
11.5
—
10
—
9.04
—
ns
405
Input data setup time
before clock rising edge
(internal clock)
t
SCC
/4 + 0.5
×
T
C
+ 25.0
47.5
—
45.5
—
43.8
—
41.32
—
ns
406
Input data not valid
before clock rising edge
(internal clock)
t
SCC
/4 + 0.5
×
T
C
5.5
—
17.0
—
15.0
—
13.8
—
10.81
ns
407
Clock falling edge to
output data valid (external
clock)
—
32.0
—
32.0
—
32.0
—
32.0
ns
408
Output data hold after
clock rising edge
(external clock)
T
C
+ 8.0
13.0
—
12.6
—
12.2
—
11.64
—
ns
409
Input data setup time
before clock rising edge
(external clock)
0.0
—
0.0
—
0.0
—
0.0
—
ns
410
Input data hold time after
clock rising edge
(external clock)
9.0
—
9.0
—
9.0
—
9.0
—
ns
411
Asynchronous clock cycle
t
ACC3
64
×
T
C
320.0
—
291.2
—
266.9
—
232.0
—
ns
412
Clock low period
t
ACC
/2
10.0
150.0
—
135.6
—
123.5
—
106.0
—
ns
413
Clock high period
t
ACC
/2
10.0
150.0
—
135.6
—
123.5
—
106.0
—
ns
414
Output data setup to
clock rising edge (internal
clock)
t
ACC
/2
30.0
130.0
—
115.6
—
103.5
—
86.0
—
ns
415
Output data hold after
clock rising edge (internal
clock)
t
ACC
/2
30.0
130.0
—
115.6
—
103.5
—
86.0
—
ns
Notes:
1.
2.
3.
V
CCQH
= 3.3 V
±
0.3 V, V
CCQL
= 1.6 V
±
0.1 V; T
J
=
–40°C to +100 °C, C
L
= 50 pF.
t
SCC
= synchronous clock cycle time (for internal clock, t
SCC
is determined by the SCI clock control register and T
C
).
t
ACC
= asynchronous clock cycle time; value given for 1X Clock mode (for internal clock, t
ACC
is determined by the SCI clock
control register and T
C
).
In the timing diagrams that follow, the SCLK is drawn using the clock falling edge as a the first reference. Clock polarity is
programmable in the SCI Control Register (SCR). Refer to the DSP56321 Reference Manual for details.
4.
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