參數(shù)資料
型號(hào): DSP56321VL240
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類: 數(shù)字信號(hào)處理
英文描述: 24-Bit Digital Signal Processor
中文描述: 24位數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 74/84頁(yè)
文件大?。?/td> 898K
代理商: DSP56321VL240
DSP56321 Technical Data, Rev. 11
A-10
Freescale Semiconductor
Power Consumption Benchmark
M_TLR0 EQU $FFFF8E
M_TCPR0 EQU $FFFF8D
M_TCR0 EQU $FFFF8C
; TIMER0 Load Reg
; TIMER0 Compare Register
; TIMER0 Count Register
; Register Addresses Of TIMER1
M_TCSR1 EQU $FFFF8B
M_TLR1 EQU $FFFF8A
M_TCPR1 EQU $FFFF89
M_TCR1 EQU $FFFF88
; TIMER1 Control/Status Register
; TIMER1 Load Reg
; TIMER1 Compare Register
; TIMER1 Count Register
; Register Addresses Of TIMER2
M_TCSR2 EQU $FFFF87
M_TLR2 EQU $FFFF86
M_TCPR2 EQU $FFFF85
M_TCR2 EQU $FFFF84
M_TPLR EQU $FFFF83
M_TPCR EQU $FFFF82
; TIMER2 Control/Status Register
; TIMER2 Load Reg
; TIMER2 Compare Register
; TIMER2 Count Register
; TIMER Prescaler Load Register
; TIMER Prescalar Count Register
; Timer Control/Status Register Bit Flags
M_TE EQU 0
M_TOIE EQU 1
M_TCIE EQU 2
M_TC EQU $F0
M_INV EQU 8
M_TRM EQU 9
M_DIR EQU 11
M_DI EQU 12
M_DO EQU 13
M_PCE EQU 15
M_TOF EQU 20
M_TCF EQU 21
; Timer Enable
; Timer Overflow Interrupt Enable
; Timer Compare Interrupt Enable
; Timer Control Mask (TC0-TC3)
; Inverter Bit
; Timer Restart Mode
; Direction Bit
; Data Input
; Data Output
; Prescaled Clock Enable
; Timer Overflow Flag
; Timer Compare Flag
; Timer Prescaler Register Bit Flags
M_PS EQU $600000
M_PS0 EQU 21
M_PS1 EQU 22
; Prescaler Source Mask
;
M_TC0 EQU 4
M_TC1 EQU 5
M_TC2 EQU 6
M_TC3 EQU 7
Timer Control Bits
; Timer Control 0
; Timer Control 1
; Timer Control 2
; Timer Control 3
;------------------------------------------------------------------------
;
; EQUATES for Direct Memory Access (DMA)
;
;------------------------------------------------------------------------
; Register Addresses Of DMA
M_DSTR EQU FFFFF4
M_DOR0 EQU $FFFFF3
M_DOR1 EQU $FFFFF2
M_DOR2 EQU $FFFFF1
M_DOR3 EQU $FFFFF0
; DMA Status Register
; DMA Offset Register 0
; DMA Offset Register 1
; DMA Offset Register 2
; DMA Offset Register 3
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