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參數(shù)資料
| 型號： | DSP56321VL240 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 24-Bit Digital Signal Processor |
| 中文描述： | 24位數(shù)字信號處理器 |
| 文件頁數(shù)： | 10/84頁 |
| 文件大?。?/td> | 898K |
| 代理商： | DSP56321VL240 |
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DSP56321 Technical Data, Rev. 11
1-4
Freescale Semiconductor
Signals/Connections
1.4 External Memory Expansion Port (Port A)
Note:
When the DSP56321 enters a low-power standby mode (stop or wait), it releases bus mastership and tri-
states the relevant Port A signals:
A[0–17]
,
D[0–23]
,
AA[0
–
3]
,
RD
,
WR
,
BB
.
1.4.1
External Address Bus
1.4.2
External Data Bus
1.4.3
External Bus Control
Table 1-5.
External Address Bus Signals
Signal Name
Type
State During
Reset, Stop,
or Wait
Signal Description
A[0–17]
Output
Tri-stated
Address Bus
—When the DSP is the bus master, A[0–17] are active-high
outputs that specify the address for external program and data memory
accesses. Otherwise, the signals are tri-stated. To minimize power dissipation,
A[0–17] do not change state when external memory spaces are not being
accessed.
Table 1-6.
External Data Bus Signals
Signal Name
Type
State During
Reset
State During
Stop or Wait
Signal Description
D[0–23]
Input/ Output
Ignored Input
Last state:
Input: Ignored
Output:
Last value
Data Bus
—When the DSP is the bus master, D[0–23] are
active-high, bidirectional input/outputs that provide the
bidirectional data bus for external program and data
memory accesses. Otherwise, D[0–23] drivers are tri-
stated. If the last state is output, these lines have weak
keepers to maintain the last output state if all drivers are tri-
stated.
Table 1-7.
External Bus Control Signals
Signal Name
Type
State During
Reset, Stop, or
Wait
Signal Description
AA[0–3]
Output
Tri-stated
Address Attribute
—When defined as AA, these signals can be used as chip
selects or additional address lines. The default use defines a priority scheme
under which only one AA signal can be asserted at a time. Setting the AA priority
disable (APD) bit (Bit 14) of the Operating Mode Register, the priority
mechanism is disabled and the lines can be used together as four external lines
that can be decoded externally into 16 chip select signals.
RD
Output
Tri-stated
Read Enable
—When the DSP is the bus master, RD is an active-low output that
is asserted to read external memory on the data bus (D[0–23]). Otherwise, RD is
tri-stated.
WR
Output
Tri-stated
Write Enable
—When the DSP is the bus master, WR is an active-low output
that is asserted to write external memory on the data bus (D[0–23]). Otherwise,
the signals are tri-stated.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DSP56321VL275 | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 24 BIT DSP PBFREE RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| DSP56321VL275 | 制造商:Freescale Semiconductor 功能描述:Digital Signal Processor (DSP) IC |
| DSP56362 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56362AD | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:24-Bit Audio Digital Signal Processor |
| DSP56362D | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:24-Bit Audio Digital Signal Processor |
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