參數(shù)資料
型號(hào)： DSP56004FJ81
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS
中文描述： Symphony音頻DSP系列的24位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 31/82頁(yè)
文件大?。?/td> 636K
代理商： DSP56004FJ81
Specifications
RESET, Stop, Mode Select, and Interrupt Timing
MOTOROLA
DSP56004/D, Rev. 3
2-7
RESET, STOP, MODE SELECT, AND INTERRUPT TIMING
Table 2-7
Reset, Stop, Mode Select, and Interrupt Timing (C
L
= 50 pF + 2 TTL Loads)
No.
Characteristics
All frequencies
Unit
Min
Max
10
Minimum RESET assertion width:
PLL disabled
PLL enabled
1
25
×
T
C
2500
×
ET
C
21
—
—
ns
ns
14
Mode Select Setup Time
—
ns
15
Mode Select Hold Time
0
—
ns
16
Minimum Edge-triggered Interrupt Request Assertion
Width
13
—
ns
16a Minimum Edge-triggered Interrupt Request
Deassertation Width
13
—
ns
18 Delay from IRQA, IRQB, NMI Assertion to GPIO Valid
Caused by First Interrupt Instruction Execution
12
×
T
C
+ T
H
—
ns
22
Delay from General Purpose Output Valid to Interrupt
Request Deassertation for Level Sensitive Fast
Interrupts—If Second Interrupt Instruction is:
2
Single Cycle
Two Cycles
T
L
– 31
(2
×
T
C
) + T
L
– 31
—
ns
ns
25
Duration of IRQA Assertion for Recovery from Stop State
12
ns
27
Duration for Level Sensitive IRQA Assertion to ensure
interrupt service (when exiting “Stop”)
Stable External Clock, OMR Bit 6 = 1
Stable External Clock, PCTL Bit 17 = 1
6
×
T
C
+ T
L
12
—
—
ns
ns
Note:
1.
This timing requirement is sensitive to the quality of the external PLL capacitor connected to the PCAP
pin. For capacitor values
≤
2 nF, asserting RESET according to this timing requirement will ensure
proper processor initialization for capacitors with a
C/ C <
0.5%. (This is typical for ceramic
capacitors.) For capacitor values > 2 nF, asserting RESET according to this timing requirement will
ensure proper processor initialization for capacitors with a
C/ C < 0.01%. (This is typical for Teflon,
polystyrene, and polypropylene capacitors.) However, capacitors with values > 2 nF with a
C/ C > 0.01% may require longer RESET assertion to ensure proper initialization.
When using fast interrupts and IRQA and IRQB are defined as level-sensitive, then timing 22 applies to
prevent multiple interrupt service. To avoid these timing restrictions, the Negative Edge-triggered
mode is recommended when using fast interrupts. Long interrupts are recommended when using
Level-sensitive mode.
2.
Figure 2-2
Reset Timing
RESET
10
V
IHR
AA0251
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關(guān)PDF資料
PDF描述
DSP56004ROM SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS
DSP56721 SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSPA56720AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSPA56721AF SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
DSPA56721AG SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56004ROM 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS
DSP56004UM 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:DSP56004 24-Bit Digital Signal Processor User＇s Manual Revision 1
DSP56004UM/AD 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS
DSP56005DS 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:DSP56005 24-Bit Digital Signal Processor Datasheet
DSP56005UM 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:DSP56005 24-Bit Digital Signal Processor User＇s Manual
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