參數(shù)資料
型號(hào)： DSP56004FJ81
廠(chǎng)商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS
中文描述： Symphony音頻DSP系列的24位數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 18/82頁(yè)
文件大?。?/td> 636K
代理商： DSP56004FJ81
1-12
DSP56004/D, Rev. 3
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Signal/Connection Descriptions
Serial Host Interface (SHI)
SS
HA2
Input
Input
Tri-stated
SPI Slave Select (SS)
—This signal is an active low
Schmitt-trigger input when configured for the SPI
mode. When configured for the SPI Slave mode, this
signal is used to enable the SPI slave for transfer.
When configured for the SPI Master mode, this
signal should be kept deasserted. If it is asserted
while configured as SPI master, a bus error
condition will be flagged.
I
2
C Slave Address 2 (HA2)
—This signal uses a
Schmitt-trigger input when configured for the I
2
C
mode. When configured for the I
2
C Slave mode, the
HA2 signal is used to form the slave device address.
HA2 is ignored in the I
2
C Master mode. If SS is
deasserted, the SHI ignores SCK clocks and keeps
the MISO output signal in the high-impedance
state.
Note:
This signal is tri-stated during hardware reset,
software reset, or individual reset (no need for
external pull-up in this state).
HREQ
Input or
Output
Tri-stated
Host Request
—This signal is an active low Schmitt-
trigger input when configured for the Master mode, but
an active low output when configured for the Slave
mode. When configured for the Slave mode, HREQ is
asserted to indicate that the SHI is ready for the next data
word transfer and deasserted at the first clock pulse of
the new data word transfer. When configured for the
Master mode, HREQ is an input and when asserted by
the external slave device, it will trigger the start of the
data word transfer by the master. After finishing the data
word transfer, the master will await the next assertion of
HREQ to proceed to the next transfer.
Note:
This signal is tri-stated during hardware, software,
individual reset, or when the HREQ[1:0] bits (in the
HCSR) are cleared (no need for external pull-up in this
state).
Table 1-8
Serial Host Interface (SHI) signals (Continued)
Signal Name
Signal
Type
State
during
Reset
Signal Description
F
Freescale Semiconductor, Inc.
n
.
相關(guān)PDF資料
PDF描述
DSP56004ROM SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS
DSP56721 SymphonyTM DSP56720 / DSP56721 Multi-Core Audio Processors
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DSP56004ROM 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS
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DSP56004UM/AD 制造商:FREESCALE 制造商全稱(chēng):Freescale Semiconductor, Inc 功能描述:SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS
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