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參數(shù)資料
| 型號： | DSP56004FJ81 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | Symphony音頻DSP系列的24位數(shù)字信號處理器 |
| 文件頁數(shù)： | 24/82頁 |
| 文件大?。?/td> | 636K |
| 代理商： | DSP56004FJ81 |
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1-18
DSP56004/D, Rev. 3
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
Signal/Connection Descriptions
On-Chip Emulation (OnCE
TM
) Port
DR
Input
Debug Request (DR)
—The debug request input provides a
means of entering the Debug mode of operation. This signal,
when asserted (pulled low), will cause the DSP to finish the
current instruction being executed, to save the instruction
pipeline information, to enter the Debug mode, and to wait
for commands to be entered from the debug serial input line.
While the DSP is in the Debug mode, the user can reset the
OnCE port controller by asserting DR, waiting for an
acknowledge pulse on DSO, and then deasserting DR. It
may be necessary to reset the OnCE port controller in cases
where synchronization between the OnCE port controller
and external circuitry is lost. Asserting DR when the DSP is
in the Wait or the Stop mode, and keeping it asserted until
an acknowledge pulse in the DSP is produced, puts the DSP
into the Debug mode. After receiving the acknowledge
pulse, DR must be deasserted before sending the first OnCE
port command. For more information, see Methods Of
Entering The Debug Mode
in the
DSP56000 Family
Manual
.
Note:
If the OnCE port is not in use, an external pull-up resistor
should be attached to the DR line.
Table 1-12
On-Chip Emulation Port Signals (Continued)
Signal
Name
Signal
Type
State during
Reset
Signal Description
F
Freescale Semiconductor, Inc.
n
.
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| DSP56004ROM | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:SYMPHONY AUDIO DSP FAMILY 24-BIT DIGITAL SIGNAL PROCESSORS |
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