參數(shù)資料
型號: DS87C550-FNL
英文描述: EPROM High-Speed Micro with A/D and PWM
中文描述: 存儲器高速微與A / D及PWM
文件頁數(shù): 29/50頁
文件大?。?/td> 763K
代理商: DS87C550-FNL
DS87C550
29 of 50
WATCHDOG TIMEOUT VALUES
Table 8
INTERRUPT TIMEOUT (CLOCKS)
4X/
2X
CD1:0
WD1:0=00
1
00
2
15
0
00
2
16
x
01
2
17
x
10
2
17
x
11
2
25
RESET TIME-CLOCKS
WD1:0=01
2
18
+512
2
19
+512
2
20
+512
2
20
+512
2
28
+512
WD1:0=01
2
18
2
19
2
20
2
20
2
28
WD1:0=10
2
21
2
22
2
23
2
23
2
31
WD1:0=11
2
24
2
25
2
26
2
26
2
34
WD1:0=00
2
15
+512
2
16
+512
2
17
+512
2
17
+512
2
25
+512
WD1:0=10
2
21
+512
2
22
+512
2
23
+512
2
23
+512
2
31
+512
WD1:0=11
2
24
+512
2
25
+512
2
26
+512
2
26
+512
2
34
+512
The watchdog timer uses the internal system clock as a time base so its timeout periods are very accurate.
From the table, it can be seen that for a 33 MHz crystal frequency, the watchdog timer is capable of
producing timeout periods from 3.97 ms (2
17
* 1/33 MHz) to over two seconds (2.034 = 2
26
* 1/33 MHz)
with the default setting of CD1:0 (=10). This wide variation in timeout periods allows very flexible
system implementation.
In a typical initialization, the user selects one of the possible counter values to determine the timeout.
Once the counter chain has completed a full count, hardware will set the interrupt flag
(WDIF=WDCON.3). There is no hardware support for a watchdog interrupt, but this flag may be polled
to determine if the timeout period has been completed. Regardless of whether the software makes use of
this flag, there are then 512 clocks left until the reset flag (WTRF=WDCON.2) is set. Software can
enable (1) or disable (0) the reset using the Enable Watchdog Reset (EWT=WDCON.1) bit. Note that the
watchdog is a free running timer and does not require an enable.
POWER-FAIL RESET
The DS87C550 incorporates an internal precision band-gap voltage reference which, when coupled with a
comparator circuit, provides a full power-on and power-fail reset function. This circuit monitors the
processor’s incoming power supply voltage (V
CC
) and holds the processor in reset while V
CC
is out of
tolerance. Once V
CC
has risen above V
RST
, the DS87C550 will restart the oscillator for the external
crystal and count 65,536 clock cycles before program execution begins at location 0000h. This power
supply monitor will also invoke the reset state when V
CC
drops below the threshold condition. This reset
condition will remain while power is below the minimum voltage level. When power exceeds the reset
threshold, a full power-on reset will be performed. In this way, this internal voltage monitoring circuitry
handles both power-up and power down conditions without the need for additional external components.
The processor exits the reset condition automatically once V
CC
meets V
RST
. This helps the system
maintain reliable operation by only permitting processor operation when its supply voltage is in a known
good state. Software can determine that a Power-On Reset has occurred by checking the Power-On Reset
flag (POR=WDCON.6). Software should clear the POR bit after reading it.
The Reset pin of the DS87C550 is both an input and an output. When the processor is being held in reset
by the power-fail detection circuitry, the reset pin will be actively pulled high by the processor, and can
therefore be used as an input to other external devices.
POWER-FAIL INTERRUPT
The band-gap voltage reference that sets a precise reset threshold also generates an optional early warning
Power-fail Interrupt (PFI). When enabled by software, the processor will vector to ROM address 0033h if
V
CC
drops below V
PFW
. PFI has the highest priority. The PFI enable is in the Watchdog Control SFR
(EPFI=WDCON.5). Setting this bit to a logic 1 will enable the PFI. Application software can also read
the PFI flag at WDCON.4. A PFI condition sets this bit to a 1. The flag is independent of the interrupt
enable and software must manually clear it.
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