參數(shù)資料
型號(hào)： DS87C550-FNL
英文描述： EPROM High-Speed Micro with A/D and PWM
中文描述： 存儲(chǔ)器高速微與A / D及PWM
文件頁(yè)數(shù)： 27/50頁(yè)
文件大?。?/td> 763K
代理商： DS87C550-FNL
DS87C550
27 of 50
When the LSB of timer/counter 2 (TL2) overflows, flag TF2B (T2SEL.4) is set, and flag TF2 (T2CON.7)
is set when the high byte (TH2) overflows. Setting flag TF2 also sets flag TF2B. Even though only one
interrupt is available for Timer 2, either or both of these overflows can be programmed to request an
interrupt. To enable the interrupt, the Timer 2 interrupt enable bit ET2 (EIE.7) must be set to a 1. The 8-
bit overflow interrupt or the 16-bit overflow interrupt is then individually enabled by setting TF2BS
(T2SEL.6) or TF2S (T2SEL.7). Since there is only one interrupt vector for both possible Timer 2
interrupts, the interrupt service routine must determine which event caused the interrupt by polling the
available flags. For both interrupt flags, software must clear them upon servicing the interrupt. There is
no automatic hardware clearing of these flags.
TIMER 2 CAPTURE FEATURE
One of the new features added to Timer 2 is the capture function. The output of Timer 2 is available to
four independent 16-bit capture register pairs (CPTH3:CPTL3, CPTH2:CPTL2, CPTH1:CPTL1, &
CPTH0:CPTL0). These registers are loaded with the 16-bit value contained in Timer 2 when transitions
occur on the corresponding input pin INT5/CT3, INT4/CT2, INT3/CT1 or INT2/CT0 (P1.3, P1.2, P1.1,
or P1.0) respectively. When the capture function is not being used, these input pins also serve as external
interrupt inputs. The Capture Trigger Control register (CTCON) can be programmed to make the capture
occur on a rising edge, a falling edge, or on either a rising or a falling edge on these input pins. The
functionality of the CTCON register is illustrated below. Note that the edge sensitivity established by the
setting of CTCON bits applies to both the capture function and the external interrupt function of these
input pins. This addition allows maximum flexibility in selecting interrupt polarity. Whether these input
pins are used as external interrupt inputs or as capture commands, the input will set the appropriate flag in
the External Interrupt Flag register (T2IR.3:0) and will create an interrupt if the associated enable in the
Extended Interrupt Enable (EIE.3:0) register is set.
CTCON REGISTER FUNCTIONALITY
Capture register 3 triggered by a falling edge on INT5/CT3
Capture register 3 triggered by a rising edge on INT5/CT3
Capture register 2 triggered by a falling edge on INT4/CT2
Capture register 2 triggered by a rising edge on INT4/CT2
Capture register 1 triggered by a falling edge on INT3/CT1
Capture register 1 triggered by a rising edge on INT3/CT1
Capture register 0 triggered by a falling edge on INT2/CT0
Capture register 0 triggered by a rising edge on INT2/CT0
CTCON.7
CTCON.6
CTCON.5
CTCON.4
CTCON.3
CTCON.2
CTCON.1
CTCON.0
CT3
CT3
CT2
CT2
CT
CT1
1
CT0
CT0
TIMER 2 COMPARE FEATURE
Another new feature added to Timer 2 capabilities is the compare function. Prior to enabling this
function, the associated compare register pair (CMPH0:CMPL0, CMPH1:CMPL1, CMPH2:CMPL2) is
loaded by software with a 16-bit number. Each time Timer 2 is incremented, the contents of these
registers are compared with the new value of the timer. When a match occurs, the corresponding interrupt
flag (T2IR.6:4) is set to a 1 on the next machine cycle and an interrupt will occur if the corresponding
enable bit is set in the Extended Interrupt Enable (EIE.6:4) register. When a match with CMPH0:CMPL0
occurs, port pins P4.0 through P4.5 are set to a 1 if the corresponding bits of the Set Enable register
(SETR) are at logic 1. If the match is with CMPH1:CMPL1, port pins P4.0 through P4.5 are reset to 0
when the corresponding bits in the reset/toggle enable register RSTR are at logic 1. A match with
CMPH2:CMPL2 toggles port pins P4.6 and 4.7 if the corresponding bits in the RSTR register are at logic
1. Note that for the toggle function it is not the port pin latch that is actually toggled. Instead, separate
flip-flops output the SFR bits TGFF1 and TGFF0 that actually determine the state of the respective port
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
DS87C550-KCL 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM
DS87C550-QCL 制造商:DALLAS 制造商全稱:Dallas Semiconductor 功能描述:EPROM High-Speed Micro with A/D and PWM
DS87C550-QCL+ 功能描述:IC MCU EPROM ADC/PWM HS 68-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:87C 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:260 系列:73S12xx 核心處理器:80515 芯體尺寸:8-位 速度:24MHz 連通性:I²C，智能卡，UART/USART，USB 外圍設(shè)備:LED，POR，WDT 輸入/輸出數(shù):9 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-VFQFN 裸露焊盤 包裝:管件
DS87C550-QCW 制造商:Maxim Integrated Products 功能描述:DS87C550 WAIVERED FOR LS & MARKING - Rail/Tube
DS87C550-QNL 功能描述:IC MCU EPROM ADC/PWM HS 68-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:87C 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:260 系列:73S12xx 核心處理器:80515 芯體尺寸:8-位 速度:24MHz 連通性:I²C，智能卡，UART/USART，USB 外圍設(shè)備:LED，POR，WDT 輸入/輸出數(shù):9 程序存儲(chǔ)器容量:64KB（64K x 8） 程序存儲(chǔ)器類型:閃存 EEPROM 大小:- RAM 容量:2K x 8 電壓 - 電源 (Vcc/Vdd):2.7 V ~ 5.5 V 數(shù)據(jù)轉(zhuǎn)換器:- 振蕩器型:內(nèi)部 工作溫度:-40°C ~ 85°C 封裝/外殼:68-VFQFN 裸露焊盤 包裝:管件
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