參數(shù)資料
型號: DS80C411-FNY+
廠商: Maxim Integrated Products
文件頁數(shù): 68/102頁
文件大?。?/td> 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 90
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 75MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 64
程序存儲器容量: 64KB(64K x 8)
程序存儲器類型: ROM
RAM 容量: 64K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
68 of 102
Transmit/Receive Packet Buffer Memory (8kB)
The DS80C410 Ethernet controller uses 8kB of internal SRAM as transmit/receive packet buffer memory. This
SRAM is read/write accessible as data memory by the CPU using the MOVX instruction. The BCU also has access
to this SRAM, and automatically writes/reads packet buffer memory whenever it needs to store or retrieve Ethernet
packet information. The logical MOVX address range of the 8kB SRAM is fixed at FFE000h to FFFFFFh.
When used for Ethernet packet buffer memory, the 8kB SRAM is logically configured into (32) pages of 64 words
each, where a word consists of 4 Bytes. These 32 pages can be dynamically allocated between Ethernet transmit
and receive buffer memory. The five least significant bits of the Ethernet buffer size (EBS; E5h) SFR specify how
many pages are allocated for receive buffer memory. The remaining pages of the 32 are used as transmit buffer
memory. Note that transmit and receive data packets can span multiple pages. The reset default state of the
Ethernet buffer size select bits (EBS.4–EBS.0) is 00000b, which configures all 32 pages as transmit buffer
memory. As an example, setting EBS.4–EBS.0 = 10000b would result in pages 0–15 (16 pages) being configured
as receive buffer memory and pages 16–31 (16 pages) being configured as transmit buffer memory. A setting of
11111b leaves a single page (page 31) for transmit buffer memory and configures pages 0–30 (31 pages) as
receive buffer memory. Changing the transmit/receive buffer-size settings flush the contents of the receive buffer
and the receive FIFO. Figure 11 is an illustration of the 8kB buffer memory map and addressing scheme.
Figure 11. Transmit/Receive Data Buffer Memory
EXAMPLE: PAGE 1, WORD 2, BYTE 3
WORD 2
WORD 63
.
STATUS WORD (WORD 0)
WORD 1
.
PAGE 31
PAGE (n - 2)
PAGE (n - 1)
PAGE n
PAGE 0
PAGE 1
RECEIVE
BUFFER
(n PAGES)
TRANSMIT
BUFFER
(32 - n PAGES)
BUFFER SIZE
SETTING
(EBS.4–EBS.0)
FIXED
PAGE
WORD
BYTE
8kB INTERNAL SRAM
PAGE 1
11111111 111
00001
000010
11
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參數(shù)描述
DS80C411-FNY+ 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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