參數(shù)資料
型號(hào)： DS80C411-FNY+
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 37/102頁(yè)
文件大?。?/td> 0K
描述： IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 90
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 75MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： ROM
RAM 容量： 64K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
DS80C410/DS80C411 Network Microcontrollers with Ethernet and CAN
4 of 102
AC ELECTRICAL CHARACTERISTICS (MULTIPLEXED ADDRESS/DATA BUS)
(VCC3 = 3.0V to 3.6V, VCC1 = 1.8V ±10%, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
75MHz
VARIABLE CLOCK
UNITS
MIN
MAX
MIN
MAX
External Crystal Frequency
1 / tCLK
4
40
MHz
Clock Mutliplier 2X Mode
Clock Multiplier 4X Mode
16
37.5
11
18.75
External Clock Oscillator Frequency
1 / tCLK
DC
75
MHz
Clock Mutliplier 2X Mode
16
37.5
Clock Multiplier 4X Mode
11
18.75
ALE Pulse Width
tLHLL
15.0
tCLCL + tCHCL - 5
ns
Port 0 Instruction Address Valid to ALE Low
tAVLL
1.7
tCHCL - 5
ns
Address Hold After ALE Low
tLLAX
4.7
tCLCH - 2
ns
ALE Low to Valid Instruction In
tLLIV
14.3
2tCLCL + tCLCH - 19
ns
ALE Low to PSEN Low
tLLPL
3.7
tCLCH - 3
ns
PSEN
Pulse Width
tPLPH
21.7
2tCLCL - 5
ns
PSEN
Low to Valid Instruction In
tPLIV
8.7
2tCLCL -18
ns
Input Instruction Hold After PSEN
tPXIX
0
ns
Input Instruction Float After PSEN
tPXIZ
8.3
tCLCL - 5
ns
Port 0 Address to Valid Instruction In
tAVIV0
21.0
3tCLCL - 19
ns
Port 2, 4, 6 Address or Port 4 CE to Valid
Instruction In
tAVIV2
24.7
3tCLCL + tCLCH - 22
ns
PSEN
Low to Address Float
tPLAZ
0
ns
Note 1:
AC electrical characteristics assume 50% duty cycle for the oscillator, oscillator frequency ≤ 75MHz, and are not 100% production
tested, but are guaranteed by design.
Note 2:
All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 3:
tCLCL, tCLCH, tCHCL are time periods associated with the internal system clock and are related to the external clock (tCLK) as defined in
the External Clock Oscillator (XTAL1) Characteristics table.
Note 4:
The precalculated 75MHz MIN/MAX timing specifications assume an exact 50% duty cycle.
Note 5:
All signals guaranteed with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7 (
PCE0-3
), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
Note 6:
For high-frequency operation, special attention should be paid to the float times of the interfaced memory devices so as to avoid
bus contention.
Note 7:
References to the XTAL, XTAL1 or CLK signal in timing diagrams is to assist in determining the relative occurrence of events, not
for determing absolute signal timing with respect to the external clock.
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DS80C411-FNY+ 功能描述:8位微控制器 -MCU Network MCU w/Ethernet & CAN RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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