參數(shù)資料
型號(hào): DS80C400-FNY
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 59/97頁(yè)
文件大?。?/td> 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 75MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 64
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: ROM
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
配用: DS80C400-KIT#-ND - EVAL KIT FOR DS80C400
DS80C400 Network Microcontroller
62 of 97
Address Check Block
The address check block of the Ethernet controller monitors the destination address of all incoming packets and
determines whether the address passes or fails the filter criteria configured by CPU. The outcome of this address
filter test, along with bits signaling whether the frame is a broadcast or multicast frame, is reported by the BCU in a
packet’s receive status word.
All incoming frames can be classified as one of three types: unicast, multicast, or broadcast (a special type of
multicast). A unicast frame contains a 0 in the first received bit of the destination address and is intended for a
single node on the network. A multicast frame contains a 1 in the first received bit of the destination address and is
intended for multiple devices on the network. A broadcast frame is a multicast frame containing all 1’s in the
destination address field and is intended for all network devices. Unless specifically disabled through the disable
broadcast frame (DBF) bit in the CSR MAC control register (00h), broadcast frames are always received by the
DS80C400 MAC.
The address filter criteria is established using five bits found in the CSR MAC control register (00h). Three basic
filter possibilities exist: perfect, inverse, and hash. Perfect filtering requires that the destination address perfectly
match the MAC physical address that has been assigned in CSR registers MAC address high (04h) and MAC
address low (08h). Inverse filtering requires that the destination address be anything other than the assigned MAC
physical address. Perfect and inverse filtering are only applied to unicast frames. Hash filtering uses a user-defined
hash table contained in CSR registers multicast address high (0Ch) and multicast address low (10h) to detect a
successful address match. Figure 7 shows the five bits controlling the destination address filter. Table 15 gives the
valid bit combinations and resultant filter modes. Note that some of the address filter mode control bits can instruct
the address check block to automatically pass or fail certain types of frames.
Figure 7. Address Filter Mode Control Bits
CSR Register MAC Control (00h)
31
0
HP (MAC Control.13) Hash/Perfect Filtering Mode
HO (MAC Control.15) Hash-Only Filtering Mode
IF (MAC Control.17) Inverse Filtering
PR (MAC Control.18) Promiscuous Mode
PM (MAC Control.19) Pass All Multicast
Table 15. Address Filter Modes
FILTER MODE CONTROL BITS
DESTINATION ADDRESS FILTER CRITERIA
PM
PR
IF
HO
HP
UNICAST
MULTICAST
0
PERFECT
FAIL
0
1
0
INVERSE
FAIL
0
1
PERFECT
HASH
1
0
x
PERFECT
PASS
0
1
HASH
1
0
1
HASH
PASS
x
1
0
x
PASS (reset default state = 01000b)
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DS80C400-FNY+ 功能描述:8位微控制器 -MCU Network MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時(shí)鐘頻率:50 MHz 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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