參數(shù)資料
型號(hào): DS80C400-FNY
廠商: Maxim Integrated Products
文件頁數(shù): 57/97頁
文件大?。?/td> 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 75MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 64
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類型: ROM
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤
配用: DS80C400-KIT#-ND - EVAL KIT FOR DS80C400
DS80C400 Network Microcontroller
60 of 97
Media Independent Interface (MII)
The DS80C400 contains an IEEE 802.3 MII-compliant PHY interface. This interface contains two basic blocks. The
MII I/O block provides independent transmit and receive data-path I/O and PHY network-status signal inputs. The
MII management block implements a 2-wire serial communication bus to facilitate PHY register access. The block
diagram in Figure 4 shows the signals associated with the DS80C400 MII.
Figure 4. MII Block Diagram
MII Management Block
The MII management block allows the host to write control data to and read status from any of 32 registers in any
of 32 PHY controllers. The MII management block communicates with external PHY(s) over a 2-wire serial
interface composed of the MDC serial-clock output pin and the MDIO pin that serves as the I/O line for all address
and data transactions. Data (MDIO) is valid on the rising edge of clock (MDC). The MII address (14h) and MII data
(18h) CSR registers, outlined previously in the CSR Register section, are used by the CPU to monitor and control
the 2-wire MII serial bus. A write to the CSR register MII address triggers the read or write operation. Figure 5
shows the MII management frame format.
Figure 5. MII Management Frame Format
PREAMBLE
(32 bits)
START
(2 bits)
OP CODE
(2 bits)
PHY ADDRESS
(5 bits)
PHY
REGISTER
(5 bits)
TURN
AROUND
(2 bits)
DATA
(16 bits)
IDLE
(1 bit)
READ
111…111
01
10
PHYA [4:0]
PHYR[4:0]
ZZ*
ZZ….ZZ*
Z
WRITE
111…111
01
PHYA [4:0]
PHYR[4:0]
10
PHYD[15:0]
Z
*During a read operation, the external PHY drives the MDIO line low for the second bit of the turnaround field to indicate proper synchronization,
and then drives the 16-bits of read data requested.
MDC
MII
MANAGEMENT
BLOCK
(SERIAL INTERFACE
BUS TO PHY)
MDIO
MII I/O BLOCK
(TRANSMIT,
RECEIVE, AND FLOW
CONTROL)
EXTERNAL
PHY
DEVICE
TX_EN
TXD[3:0]
RXCLK
RX_DV
RX_ER
RXD[3:0]
CRS
COL
TXCLK
DS80C400
NOTE: WHEN CONNECTING THE DS80C400 TO AN EXTERNAL PHY, DO NOT CONNECT THE RSTOL TO THE RESET OF THE PHY. DOING SO
MAY DISABLE THE ETHERNET TRANSMIT.
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