參數(shù)資料
型號(hào)： DS80C400-FNY
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 43/97頁(yè)
文件大?。?/td> 0K
描述： IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
產(chǎn)品變化通告： Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝： 90
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 75MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： ROM
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤
配用： DS80C400-KIT#-ND - EVAL KIT FOR DS80C400
DS80C400 Network Microcontroller
48 of 97
facilitates the conversion of 4-Byte unsigned binary integers into floating point format. Table 11 shows the
operations supported by the math accelerator and their time of execution.
Table 11. Arithmetic Accelerator Execution Times
OPERATION
RESULT
EXECUTION TIME
32-Bit/16-Bit Divide
32-Bit Quotient, 16-Bit Remainder
36 tCLCL
16-Bit/16-Bit Divide
16-Bit Quotient, 16-Bit Remainder
24 tCLCL
16-Bit/16-Bit Multiply
32-Bit Product
24 tCLCL
32-Bit Shift Left/Right
32-Bit Result
36 tCLCL
32-Bit Normalize
32-Bit Mantissa, 5-Bit Exponent
36 tCLCL
Table 12 demonstrates the procedure to perform mathematical operations using the hardware math accelerator.
The MA and MB registers must be loaded and read in the order shown for proper operation, although accesses to
any other registers can be performed between accesses to the MA or MB registers. An access to the MA, MB, or
MC registers out of sequence corrupt the operation, requiring the software to clear the MST bit to restart the math
accelerator state machine. See the descriptions of the MCNT0 and MCNT1 SFRs for details about how the shift
and normalize functions operate.
Table 12. Arithmetic Accelerator Sequencing
DIVIDE (32/16 or 16/16)
MULTIPLY (16 x 16)
Load MA with dividend LSB.
Load MA with dividend LSB + 1*.
Load MA with dividend LSB + 2*.
Load MA with dividend MSB.
Load MB with divisor LSB.
Load MB with divisor MSB.
Poll the MST bit until cleared.
(9 machine cycles for 32-bit numerator)
(6 machine cycles for 16-bit numerator)
Read MA to retrieve the quotient MSB.
Read MA to retrieve the quotient LSB + 2*
Read MA to retrieve the quotient LSB + 1*
Read MA to retrieve the quotient LSB.
Read MB to retrieve the remainder MSB.
Read MB to retrieve the remainder LSB.
Load MB with multiplier LSB.
Load MB with multiplier MSB.
Load MA with multiplicand LSB.
Load MA with multiplicand MSB.
Poll the MST bit until cleared (6 machine cycles).
Read MA for product MSB.
Read MA for product LSB + 2.
Read MA for product LSB + 1.
Read MA for product LSB.
SHIFT RIGHT/LEFT
NORMALIZE
Load MA with data LSB.
Load MA with data LSB + 1.
Load MA with data LSB + 2.
Load MA with data MSB.
Configure MCNT0/MCNT1 registers as required.
Poll the MST bit until cleared (9 machine cycles).
Read MA for result MSB.
Read MA for result LSB + 2.
Read MA for result LSB + 1.
Read MA for result LSB.
Load MA with data LSB.
Load MA with data LSB + 1.
Load MA with data LSB + 2.
Load MA with data MSB.
Configure MCNT0.4–0 = 00000b.
Poll the MST bit until cleared (9 machine cycles).
Read MA for mantissa MSB.
Read MA for mantissa LSB + 2.
Read MA for mantissa LSB + 1.
Read MA for mantissa LSB.
Read MCNT0.4–MCNT0.0 for exponent.
*Not performed for 16-bit numerator.
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