CST
參數(shù)資料
型號(hào)： DS80C400-FNY
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 45/97頁(yè)
文件大?。?/td> 0K
描述： IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
產(chǎn)品變化通告： Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝： 90
系列： 80C
核心處理器： 8051
芯體尺寸： 8-位
速度： 75MHz
連通性： 1 線，CAN，EBI/EMI，以太網(wǎng)，SIO，UART/USART
外圍設(shè)備： 電源故障復(fù)位，WDT
輸入/輸出數(shù)： 64
程序存儲(chǔ)器容量： 64KB（64K x 8）
程序存儲(chǔ)器類型： ROM
RAM 容量： 1K x 8
電壓 - 電源 (Vcc/Vdd)： 1.62 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 100-LQFP
包裝： 托盤(pán)
配用： DS80C400-KIT#-ND - EVAL KIT FOR DS80C400
DS80C400 Network Microcontroller
5 of 97
PARAMETER
SYMBOL
MIN
MAX
UNITS STRETCH VALUES
CST (MD2:0)
Data Float After RD (P3.7 or
PSEN
) High
tRHDZ
tCLCL - 5
ns
CST = 0
2tCLCL - 5
1≤ CST ≤ 3
6tCLCL - 5
4 ≤ CST ≤ 7
ALE Low to Valid Data In
tLLDV
2tCLCL + tCLCH - 19
ns
CST = 0
(4 x CST + 1) tCLCL - 19
1≤ CST ≤ 3
(4 x CST + 5) tCLCL - 19
4 ≤ CST ≤ 7
Port 0 Address to Valid Data
In
tAVDV0
3tCLCL - 19
ns
CST = 0
(4 x CST + 2)tCLCL - 19
1≤ CST ≤ 3
(4 x CST + 10)tCLCL - 19
4 ≤ CST ≤ 7
Port 2, 4, 6 Address, Port 4
CE, or Port 5 PCE to Valid
Data In
tAVDV2
3tCLCL + tCLCH - 19
ns
CST = 0
(4 x CST + 2)tCLCL + tCLCH -
19
1≤ CST ≤ 3
(4 x CST + 10)tCLCL + tCLCH -
20
4 ≤ CST ≤ 7
ALE Low to (RD or PSEN) or
WR
Low
tLLWL
tCLCH - 3
tCLCH + 6
ns
CST = 0
tCLCL - 3
tCLCL + 6
1 ≤ CST ≤ 3
5tCLCL - 3
5tCLCL + 6
4 ≤ CST ≤ 7
Port 0 Address to (RD or
PSEN
) or WR Low
tAVWL0
tCLCL - 5
ns
CST = 0
2tCLCL - 6
1 ≤ CST ≤ 3
10tCLCL - 6
4 ≤ CST ≤ 7
Port 2, 4 Address, Port 4 CE,
Port 5 PCE, to (RD or PSEN)
or WR Low
tAVWL2
tCLCL + tCLCH - 5
ns
CST = 0
2tCLCL + tCLCH - 5
1 ≤ CST ≤ 3
10tCLCL + tCLCH - 5
4 ≤ CST ≤ 7
Data Valid to WR Transition
tQVWX
0
ns
Data Hold After WR High
tWHQX
tCLCL - 4
ns
CST = 0
2CLCL - 7
1 ≤ CST ≤ 3
6tCLCL - 7
4 ≤ CST ≤ 7
RD
Low to Address Float
tRLAZ
(Note 2)
0≤ CST ≤ 7
(RD or PSEN) or WR High to
ALE
tWHLH
0
7
ns
CST = 0
tCLCL - 3
tCLCL + 4
1 ≤ CST ≤ 3
5tCLCL - 3
5tCLCL + 4
4 ≤ CST ≤ 7
(RD or PSEN) or WR High to
Port 4 CE or Port 5 PCE
High
tWHLH2
tCHCL -5
tCHCL + 13
ns
CST = 0
tCLCL + tCHCL - 5
tCLCL + tCHCL + 13
1 ≤ CST ≤ 3
5tCLCL + tCHCL - 5
5tCLCL + tCHCL + 13
4 ≤ CST ≤ 7
Note 1: Specifications to -40°C are guaranteed by design and not production tested.
Note 2: For a MOVX read operation, on the falling edge of ALE, Port 0 is held by a weak latch until overdriven by external memory.
Note 3: All parameters apply to both commercial and industrial temperature operation, unless otherwise noted.
Note 4: CST is the stretch cycle value as determined by the MD2, MD1, and MD0 bits of the CKCON register. tCLCL , tCLCH , tCHCL are time
periods associated with the internal system clock and are related to the external clock. See the System Clock Time Periods table.
Note 5: All signals characterized with load capacitance of 80pF except Port 0, Port 2, ALE, PSEN, RD, and WR with 100pF. The following
signals, when configured for memory interface, are also characterized with 100pF loading: Port 4 (CE0-3, A16–A19), Port 5.4–5.7
(PCE0-3), Port 6.0–6.5 (CE4-7, A20, A21), Port 7 (demultiplexed mode A0–A7).
Note 6: References to the XTAL, XTAL1, or CLK signal in timing diagrams are to assist in determining the relative occurrence of events, not for
determing absolute signal timing with respect to the external clock.
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