參數(shù)資料
型號(hào): DS80C400-FNY
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 24/97頁(yè)
文件大?。?/td> 0K
描述: IC MCU 75MHZ 16MB HP 100-LQFP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
產(chǎn)品變化通告: Product Discontinuation 20/Feb/2012
標(biāo)準(zhǔn)包裝: 90
系列: 80C
核心處理器: 8051
芯體尺寸: 8-位
速度: 75MHz
連通性: 1 線,CAN,EBI/EMI,以太網(wǎng),SIO,UART/USART
外圍設(shè)備: 電源故障復(fù)位,WDT
輸入/輸出數(shù): 64
程序存儲(chǔ)器容量: 64KB(64K x 8)
程序存儲(chǔ)器類(lèi)型: ROM
RAM 容量: 1K x 8
電壓 - 電源 (Vcc/Vdd): 1.62 V ~ 3.6 V
振蕩器型: 外部
工作溫度: -40°C ~ 85°C
封裝/外殼: 100-LQFP
包裝: 托盤(pán)
配用: DS80C400-KIT#-ND - EVAL KIT FOR DS80C400
DS80C400 Network Microcontroller
30 of 97
PIN
NAME
FUNCTION
59
A13
P2.2
A10 Program/Data Memory Address 10
P2.3
A11 Program/Data Memory Address 11
P2.4
A12 Program/Data Memory Address 12
P2.5
A13 Program/Data Memory Address 13
P2.6
A14 Program/Data Memory Address 14
P2.7
A15 Program/Data Memory Address 15
58
A14
57
A15
20
P3.0
Port 3, I/O. Port 3 functions as an 8-bit, bidirectional I/O port, and as an alternate interface for several resources
found on the traditional 8051. The reset condition of Port 3 is all bits at logic 1 through a weak pullup. The logic
1 state also serves as an input mode, since external circuits writing to the port can override the weak pullup.
When software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is
written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition
driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again
becomes the output (and input) high state.
Port
Alternate Function
P3.0
RXD0 Serial Port 0 Receive
P3.1
TXD0 Serial Port 0 Transmit
P3.2
INT0
External Interrupt 0
P3.3
INT1
External Interrupt 1
P3.4
T0 Timer 0 External Input
P3.5
T1/CLKO Timer 1 External Input/External Clock Output
P3.6
WR
External Data Memory Write Strobe
P3.7
RD
External Data Memory Read Strobe
21
P3.1
22
P3.2
23
P3.3
24
P3.4
25
P3.5
26
P3.6
27
P3.7
48
P4.0
Port 4, I/O. Port 4 is composed of eight pins that are user programmable as I/O, extended program memory
chip enables, or extended address lines. The configuration of the eight pins is established through the
programming of the port 4 control register (P4CNT). Following a reset, and if EA is low, P4.3 to P4.1 are driven
high and are assigned as chip enables. Port pins P4.7 to P4.4 and P4.0 are cleared to low state and are
assigned as addresses and chip enable, respectively. Additional information on external memory interfacing is
found in the port 4 control register SFR description and other sections in the High-Speed Microcontroller User’s
Guide: Network Microcontroller Supplement.
Port
Alternate Function
P4.0
CE0
Program Memory Chip Enable 0
P4.1
CE1
Program Memory Chip Enable 1
P4.2
CE2
Program Memory Chip Enable 2
P4.3
CE3
Program Memory Chip Enable 3
P4.4
A16 Program/Data Memory Address 16
P4.5
A17 Program/Data Memory Address 17
P4.6
A18 Program/Data Memory Address 18
P4.7
A19 Program/Data Memory Address 19
47
P4.1
46
P4.2
45
P4.3
44
P4.4
43
P4.5
42
P4.6
41
P4.7
35
P5.0
Port 5, I/O. Port 5 can function as an 8-bit, bidirectional I/O port, the CAN interface, Timer 3 input, and/or as
peripheral-enable signals. The reset condition of Port 5 is all bits at logic 1 through a weak pullup. The logic 1
state also serves as an input mode, since external circuits writing to the port can override the weak pullup.
When software clears any port pin to 0, the device activates a strong pulldown that remains on until either a 1 is
written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong transition
driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port once again
becomes the output (and input) high state.
Port
Alternate Function
P5.0
C0TX CAN0 Transmit Output
P5.1
C0RX CAN0 Receive Input
P5.2
T3 Timer 3 External Input
P5.3
None
P5.4
PCE0
Peripheral Chip Enable 0
P5.5
PCE1
Peripheral Chip Enable 1
P5.6
PCE2
Peripheral Chip Enable 2
P5.7
PCE3
Peripheral Chip Enable 3
34
P5.1
33
P5.2
32
P5.3
31
P5.4
30
P5.5
29
P5.6
28
P5.7
56
P6.0
Port 6, I/O. Port 6 can function as an 8-bit, bidirectional I/O port, as program and data memory address/chip-
enable signals, and/or a third serial port. The reset condition of Port 6 is all bits at logic 1 through a weak pullup.
The logic 1 state also serves as an input mode, since external circuits writing to the port can override the weak
pullup. When software clears any port pin to 0, the device activates a strong pulldown that remains on until
either a 1 is written to the port pin or a reset occurs. Writing a 1 after the port has been at 0 activates a strong
transition driver, followed by a weaker sustaining pullup. Once the momentary strong driver turns off, the port
once again becomes the output (and input) high state.
Port
Alternate Function
P6.0
CE4
Program Memory Chip Enable 4
55
P6.1
54
P6.2
53
P6.3
52
P6.4
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