參數(shù)資料
型號(hào): DS3148
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 76/89頁(yè)
文件大?。?/td> 0K
描述: IC 8CH DS3/3 FRAMER 349-BGA
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
控制器類型: DS3/E3 調(diào)幀器
接口: LIU
電源電壓: 3.135 V ~ 3.465 V
電流 - 電源: 640mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 349-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 349-HCBGA(27x27)
包裝: 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
78 of 89
11.2 Microprocessor Interface Timing
Table 11-D. Microprocessor Interface Timing
(VDD = 3.3V
±5%, TA = -40°C to +85°C.) (Figure 11-4, Figure 11-5, and Figure 11-6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Setup Time for A[11:0] Valid to
CS Active
t1
0
ns
Setup Time for
CS Active to RD, WR, or DS
Active
t2
0
ns
Delay Time from
RD or DS Active to D[7:0]
Valid
t3
65
ns
Hold Time from
RD or WR or DS Inactive to
CS Inactive
t4
0
ns
Hold Time from
CS or RD or DS Inactive to
D[7:0] Tri-State
t5
5.0
20
ns
Wait Time from
WR or DS Active to Latch
D[7:0]
t6
65
ns
D[7:0] Setup Time to
WR or DS Inactive
t7
10
ns
D[7:0] Hold Time from
WR or DS Inactive
t8
2.0
ns
A[11:0] Hold from
WR or RD or DS Inactive
t9
5.0
ns
RD, WR, or DS Inactive Time
t10
75
ns
Muxed Address Valid to ALE Falling
t11
(Note 16)
10
ns
Muxed Address Hold Time
t12
(Note 16)
10
ns
ALE Pulse Width
t13
(Note 16)
30
ns
Setup Time for ALE High or Muxed
Address Valid to
CS Active
t14
(Note 16)
0
ns
SCLK Period
t15
19
31
ns
SCLK High and Low Time
t16
7.0
ns
SCLK Duty Cycle (High/Low)
t16/t15
40
60
%
Note 16: In nonmultiplexed bus applications (Figure 11-5), ALE should be connected high. In multiplexed bus applications (Figure 11-6), A[7:0]
are normally connected to D[7:0] externally, and the falling edge of ALE latches the address.
Note 17: Whenever
CS = 0 and RD = 0 in Intel mode or CS = 0 and R/WR = 1 and DS = 0 in Motorola mode, the bidirectional data bus D[7:0] is
driven as an output.
Figure 11-4. SCLK Clock Timing
t15
t16
HIGH
t16
LOW
SCLK
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