參數(shù)資料
型號(hào)： DS3148
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 55/89頁(yè)
文件大小： 0K
描述： IC 8CH DS3/3 FRAMER 349-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
控制器類(lèi)型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 640mA
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤(pán)
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
59 of 89
Bit 7: Receive FIFO Overrun Latched (ROVRL). This latched status bit is set to 1 each time the receive FIFO
overruns. ROVRL is cleared when the host processor writes a 1 to it and is not set again until another overrun
occurs (i.e., the FIFO has been read from and then allowed to fill up again). When ROVRL is set, it can cause a
hardware interrupt to occur if the ROVRIE bit in the HSRIE register and the HDLCIE bit in the MSRIE register are
both set to 1. The interrupt is cleared when this bit is cleared or one or both of the interrupt-enable bits are cleared.
Register Name:
HSRIE
Register Description:
HDLC Status Register Interrupt Enable
Register Address:
56h
Bit #
7
6
5
4
3
2
1
0
Name
ROVRIE
RPEIE
RPSIE
RABTIE
RHWMIE
TLWMIE
TUDRIE
TENDIE
Default
0
Bit 0: Transmit Packet-End Interrupt Enable (TENDIE). This bit enables an interrupt if the TENDL bit in the
HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 1: Transmit FIFO Underrun Interrupt Enable (TUDRIE). This bit enables an interrupt if the TUDRL bit in the
HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 2: Transmit FIFO Low Watermark Interrupt Enable (TLWMIE). This bit enables an interrupt if the TLWML bit
in the HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 3: Receive FIFO High Watermark Interrupt Enable (RHWMIE). This bit enables an interrupt if the RHWML bit
in the HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 4: Receive Abort Sequence Detected Interrupt Enable (RABTIE). This bit enables an interrupt if the RABTL
bit in the HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 5: Receive Packet Start Interrupt Enable (RPSIE). This bit enables an interrupt if the RPSL bit in the HSRL
register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 6: Receive Packet-End Interrupt Enable (RPEIE). This bit enables an interrupt if the RPEL bit in the HSRL
register is set.
0 = interrupt disabled
1 = interrupt enabled
Bit 7: Receive FIFO Overrun Interrupt Enable (ROVRIE). This bit enables an interrupt if the ROVRL bit in the
HSRL register is set.
0 = interrupt disabled
1 = interrupt enabled
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