參數(shù)資料
型號(hào)： DS3148
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 22/89頁(yè)
文件大?。?/td> 0K
描述： IC 8CH DS3/3 FRAMER 349-BGA
產(chǎn)品培訓(xùn)模塊： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝： 1
控制器類型： DS3/E3 調(diào)幀器
接口： LIU
電源電壓： 3.135 V ~ 3.465 V
電流 - 電源： 640mA
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 349-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 349-HCBGA（27x27）
包裝： 托盤
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
29 of 89
7.6.1 Master Status Register (MSR)
The master status register (MSR) is a special status register that helps the host processor quickly locate changes
in device status. Each major block in the framer has a status bit in the MSR. When an alarm or event occurs in one
of these blocks, the device can be configured to set the appropriate bit in the MSR. The latched status bits in the
MSRL can also cause a hardware interrupt to occur. In both interrupt-based and polling-based device servicing
strategies, the host processor should read the ISR1 register to determine which framers need service and then
read the MSRL register of each framer that needs service to determine which blocks within the framer need
service.
Register Name:
MSR
Register Description:
Master Status Register
Register Address:
08h
Bit #
7
6
5
4
3
2
1
0
Name
LORC
LOTC
T3E3
FEAC
HDLC
BERT
COVF
N/A
Default
—
Bit 1: Counter Overflow Event (COVF). This real-time status bit is set to 1 if any of the error counters saturate
(the error counters saturate when full). This bit is cleared when the error counters are cleared. The error counters
are discussed in Section 7.8.
Bit 2: Change in BERT Status (BERT). This real-time status bit is set when any of the bits in the BSRL register
are set and the corresponding bits in the BSRIE interrupt-enable register are set. This bit is cleared when the
latched status bits in the BSRL register are cleared or the interrupt-enable bits in the BSRIE register are cleared.
The setting of this status bit can cause a hardware interrupt to occur if the BERTIE bit in the MSRIE register is set
to a 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the MSRIE register is cleared.
Bit 3: Change in HDLC Status (HDLC). This real-time status bit is set when any of the bits in the HSRL register
are set and the corresponding bits in the HSRIE interrupt-enable register are set. This bit is cleared when the
latched status bits in the HSRL register are cleared or the interrupt-enable bits in the HSRIE register are cleared.
The setting of this status bit can cause a hardware interrupt to occur if the HDLCIE bit in the MSRIE register is set
to a 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the MSRIE register is cleared.
Bit 4: Change in FEAC Status (FEAC). This real-time status bit is set when any of the bits in the FSRL register
are set and the corresponding bits in the FSRIE interrupt-enable register are set. This bit is cleared when the
latched status bits in the FSRL register are cleared or the interrupt-enable bits in the FSRIE register are cleared.
The setting of this status bit can cause a hardware interrupt to occur if the FEACIE bit in the MSRIE register is set
to a 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the MSRIE register is cleared.
Bit 5: Change in DS3/E3 Framer Status (T3E3). This real-time status bit is set when any of the bits in the
T3E3SRL register are set and the corresponding bits in the T3E3SRIE interrupt-enable register are set. This bit is
cleared when the latched status bits in the T3E3SRL register are cleared or the interrupt-enable bits in the
T3E3SRIE register are cleared. The setting of this status bit can cause a hardware interrupt to occur if the T3E3IE
bit in the MSRIE register is set to 1. The interrupt is cleared when this bit is cleared or the interrupt-enable bit in the
MSRIE register is cleared.
Bit 6: Loss-of-Transmit Clock Detected (LOTC). This real-time status bit is set when the device detects that the
TICLK input pin has not toggled for between 9 and 21 clock periods. This bit is cleared when a clock is detected at
the TICLK input. The system clock (SCLK) is used to check for the presence of the TICLK. On reset the LOTC
status bit is set for a few clock cycles and then cleared if TICLK is present.
Bit 7: Loss-of-Receive Clock Detected (LORC). This real-time status bit is set when the device detects that the
RCLK input pin has not toggled for between 9 and 21 clock periods. This bit is cleared when a clock is detected at
the RCLK input. The system clock (SCLK) checks for the presence of the RCLK. On reset the LORC status bit is
set for a few clock cycles and then cleared if RCLK is present.
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