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參數(shù)資料
| 型號： | DS28E04S-100 |
| 元件分類： | DRAM |
| 英文描述： | 4096-Bit Addressable 1-Wire EEPROM with PIO |
| 中文描述： | 4096位尋址1 - Wire EEPROM，帶有先鋒 |
| 文件頁數(shù)： | 3/36頁 |
| 文件大小： | 347K |
| 代理商： | DS28E04S-100 |
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DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
3 of 36
PARAMETER
IO PIN, 1-Wire RESET, PRESENCE DETECT CYCLE
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Standard speed, V
PUP
> 4.5V
Standard speed (Note 17)
Overdrive speed, V
PUP
> 4.5V
Overdrive speed (Note 17)
Standard speed
Overdrive speed (Note 17)
Standard speed, V
PUP
> 4.5V
Standard speed
Overdrive speed
Standard speed
Overdrive speed, V
PUP
> 4.5V
Overdrive speed (Note 17)
Standard speed, V
PUP
> 4.5V
Standard speed
Overdrive speed
480
504
48
53
15
2
1.10
1.1
0
60
8
8
64
67
8.1
640
640
80
80
60
7
3.75
7.0
1.1
240
24
26
75
75
10
Reset Low Time (Note 1)
t
RSTL
μs
Presence-Detect High
Time
t
PDH
μs
Presence-Detect Fall Time
(Notes 3, 18)
t
FPD
μs
Presence-Detect Low
Time
t
PDL
μs
Presence-Detect Sample
Time (Note 1)
t
MSP
μs
IO PIN, 1-Wire WRITE
Standard speed
Overdrive speed (Note 17)
Standard speed
Overdrive speed
60
7
5
1
120
16
15 -
2 -
Write-0 Low Time (Note 1)
t
W0L
μs
Write-1 Low Time
(Notes 1, 19)
IO PIN, 1-Wire READ
Read Low Time
(Notes 1, 20)
Read Sample Time
(Notes 1, 20)
EEPROM
Programming Current
Programming Time
Write/Erase Cycles
(Endurance)
Data Retention
t
W1L
μs
Standard speed
Overdrive speed
Standard speed
Overdrive speed
5
1
15 -
2 -
15
2
t
RL
μs
t
RL
+
t
RL
+
t
MSR
μs
I
PROG
t
PROG
(Note 21)
(Note 22)
At +25°C
At +85°C (worst case)
At +85°C (worst case)
1
10
mA
ms
200k
50k
10
N
CY
t
DR
years
Note 1:
Note 2:
Note 3:
Note 4:
System requirement.
Maximum instantaneous pulldown current through all pins combined.
Guaranteed by design, simulation only. Not production tested.
This load current is caused by the internal weak pullup, which asserts a logical 1 to address pins that are not connected. The
logical state of the address pins must not change during the execution of ROM function commands during those time slots in
which these bits are relevant.
The I-V characteristic is linear for voltages less than 1V.
Width of the narrowest pulse that trips the activity latch. Back to back pulses that are active for < t
PWMIN
(max) and that have an
intermediate inactive time < t
(max) are not guaranteed to be filtered.
The Pulse function requires that V
CC
power is available; otherwise the command will not be executed.
Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Capacitance on the data pin could be 800pF when V
PUP
is first applied. If a 2.2k resistor is used to pull up the data line, 2.5μs
after V
PUP
has been applied the parasite capacitance will not affect normal communications.
V
TL
, V
TH
, and V
HY
are a function of the internal supply voltage.
Voltage below which, during a falling edge on IO, a logic 0 is detected.
The voltage on IO needs to be less than or equal to V
whenever the master drives the line low.
Voltage above which, during a rising edge on IO, a logic 1 is detected.
After V
TH
is crossed during a rising edge on IO, the voltage on IO has to drop by at least V
HY
to be detected as logic '0'.
Applies to a single DS28E04-100 without V
supply, attached to a 1-Wire line.
The earliest recognition of a negative edge is possible at t
REH
after V
TH
has been previously reached.
Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table.
Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is
80% of V
PUP
and the time at which the voltage is 20% of V
PUP
.
represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to V
TH
.
represents the time required for the pullup circuitry to pull the voltage on IO up from V
IL
to the input high threshold of the bus
master.
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10:
Note 11:
Note 12:
Note 13:
Note 14:
Note 15:
Note 16:
Note 17:
Note 18:
Note 19:
Note 20:
相關PDF資料 |
PDF描述 |
|---|---|
| DS3151 | Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs |
| DS3151N | Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs |
| DS3152 | Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs |
| DS3152N | Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs |
| DS3153 | Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| DS28E04S-100/T | 功能描述:電可擦除可編程只讀存儲器 RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| DS28E04S-100+ | 功能描述:電可擦除可編程只讀存儲器 4096-Bit Addressable 1-Wire 電可擦除可編程只讀存儲器 w/PIO RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| DS28E04S-100+T | 功能描述:電可擦除可編程只讀存儲器 4096-Bit Addressable 1-Wire 電可擦除可編程只讀存儲器 w/PIO RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
| DS28E04S-224-BB+T | 制造商:Maxim Integrated Products 功能描述:- Tape and Reel |
| DS28E05P+ | 功能描述:電可擦除可編程只讀存儲器 1W 1KB FTP MEMORY TSOC RoHS:否 制造商:Atmel 存儲容量:2 Kbit 組織:256 B x 8 數(shù)據(jù)保留:100 yr 最大時鐘頻率:1000 KHz 最大工作電流:6 uA 工作電源電壓:1.7 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:SOIC-8 |
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