參數(shù)資料
型號(hào): DS28E04S-100
元件分類: DRAM
英文描述: 4096-Bit Addressable 1-Wire EEPROM with PIO
中文描述: 4096位尋址1 - Wire EEPROM,帶有先鋒
文件頁數(shù): 23/36頁
文件大?。?/td> 347K
代理商: DS28E04S-100
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
23 of 36
Figure 13. Hardware Configuration
BUS MASTER
Open-Drain
Port Pin
RX = RECEIVE
TX = TRANSMIT
100
MOSFET
V
PUP
RX
TX
TX
RX
DATA
R
PUP
11μA
Max.
DS28E04 1-Wire PORT
TRANSACTION SEQUENCE
The protocol for accessing the DS28E04-100 through the 1-Wire port is as follows:
Initialization
ROM Function Command
Memory/Control Function Command
Transaction/Data
INITIALIZATION
All transactions on the 1-Wire bus begin with an initialization sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the slave(s). The presence
pulse lets the bus master know that the DS28E04-100 is on the bus and is ready to operate. For more details, see
the
1-Wire Signaling
section.
1-Wire ROM FUNCTION COMMANDS
Once the bus master has detected a presence, it can issue one of the eight ROM function commands that the
DS28E04-100 supports. All ROM function commands are 8 bits long. A list of these commands follows (refer to the
flow chart in Figure 14).
READ ROM [33h]
This command allows the bus master to read the DS28E04-100’s 8-bit family code, unique 40-bit serial number, 8-
bit address byte, and 8-bit CRC. The lower order 7 bits of the address byte read back the state of the address pins
A6 to A0. See also Figure 3. This command can only be used if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code and 48-bit serial number result in a mismatch of the CRC.
Note that there will also be a CRC mismatch if one or more of the external address inputs are connected to GND.
The ROM CRC is hardcoded with A6 to A0 set to 1s. The master should comprehend this and calculate the ROM
CRC similarly.
MATCH ROM [55h]
The Match ROM command, followed by a 64-bit ROM sequence, allows the bus master to address a specific
DS28E04-100 on a multidrop bus. Only the DS28E04-100 that exactly matches the 64-bit ROM sequence,
including the external address, responds to the following Memory/Control Function command. All other slaves wait
for a reset pulse. This command can be used with a single or multiple devices on the bus.
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